[llvm] 65de98f - CostModel/RISCV: tweak test for ctpop, with/without ZVBB (#67013)

[via llvm-commits]

Author: Ramkumar Ramachandra
Date: 2023-09-27T12:16:54+01:00
New Revision: 65de98f4deecbebca59d291b4d4cc26bd884845a

URL: https://github.com/llvm/llvm-project/commit/65de98f4deecbebca59d291b4d4cc26bd884845a
DIFF: https://github.com/llvm/llvm-project/commit/65de98f4deecbebca59d291b4d4cc26bd884845a.diff

LOG: CostModel/RISCV: tweak test for ctpop, with/without ZVBB (#67013)

Vector ctpop only exists under ZVBB, but ZVBB is unaccounted for in the
cost-model of ctpop. Document this defect with an additional RUN line in
the test for ctpop, showing identical costs with/without ZVBB. A
follow-up patch could fix this defect.

Added: 
    

Modified: 
    llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll b/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
index 7bdcd477090c07c..ed850b504cda96f 100644
--- a/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
@@ -1,5 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
-; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v,+f,+d -riscv-v-vector-bits-min=-1 | FileCheck %s
+; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v,+f,+d -riscv-v-vector-bits-min=-1 | FileCheck %s --check-prefixes=CHECK,NOZVBB
+; Vector ctpop exists only under ZVBB
+; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v,+f,+d,+experimental-zvbb -riscv-v-vector-bits-min=-1 | FileCheck %s --check-prefixes=CHECK,ZVBB
 
 define void @bswap() {
 ; CHECK-LABEL: 'bswap'
@@ -849,3 +851,6 @@ declare <vscale x 2 x i64> @llvm.vp.cttz.nvx2i64(<vscale x 2 x i64>, i1 immarg,
 declare <vscale x 4 x i64> @llvm.vp.cttz.nvx4i64(<vscale x 4 x i64>, i1 immarg, <vscale x 4 x i1>, i32)
 declare <vscale x 8 x i64> @llvm.vp.cttz.nvx8i64(<vscale x 8 x i64>, i1 immarg, <vscale x 8 x i1>, i32)
 declare <vscale x 16 x i64> @llvm.vp.cttz.nvx16i64(<vscale x 16 x i64>, i1 immarg, <vscale x 16 x i1>, i32)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; NOZVBB: {{.*}}
+; ZVBB: {{.*}}