[llvm] be8b559 - [AMDGPU] Test codegen'ing True16 additions.

[Ivan Kosarev via llvm-commits]

Author: Ivan Kosarev
Date: 2023-09-27T11:10:48+01:00
New Revision: be8b559956b1c52c58a4085fa853c83596c63e95

URL: https://github.com/llvm/llvm-project/commit/be8b559956b1c52c58a4085fa853c83596c63e95
DIFF: https://github.com/llvm/llvm-project/commit/be8b559956b1c52c58a4085fa853c83596c63e95.diff

LOG: [AMDGPU] Test codegen'ing True16 additions.

The GlobalISel part is to be addressed later.

Differential Revision: https://reviews.llvm.org/D156106

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/fadd.f16.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AMDGPU/fadd.f16.ll b/llvm/test/CodeGen/AMDGPU/fadd.f16.ll
index 1ecfcf1dfa0a1a9..00f7eacaeb55507 100644
--- a/llvm/test/CodeGen/AMDGPU/fadd.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fadd.f16.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=SI %s
 ; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=VI %s
-; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=+real-true16,-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=GFX11 %s
 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
 
 define amdgpu_kernel void @fadd_f16(
@@ -74,7 +74,9 @@ define amdgpu_kernel void @fadd_f16(
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11-NEXT:    buffer_load_u16 v1, off, s[0:3], 0 glc dlc
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_add_f16_e32 v0.l, v0.l, v0.h
 ; GFX11-NEXT:    buffer_store_b16 v0, off, s[8:11], 0
 ; GFX11-NEXT:    s_nop 0
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -169,7 +171,9 @@ define amdgpu_kernel void @fadd_f16_imm_a(
 ; GFX11-NEXT:    s_mov_b32 s3, s7
 ; GFX11-NEXT:    buffer_load_u16 v0, off, s[0:3], 0
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_f16_e32 v0, 1.0, v0
+; GFX11-NEXT:    v_mov_b16_e32 v0.h, 0x3c00
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_add_f16_e32 v0.l, v0.l, v0.h
 ; GFX11-NEXT:    buffer_store_b16 v0, off, s[4:7], 0
 ; GFX11-NEXT:    s_nop 0
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -256,7 +260,9 @@ define amdgpu_kernel void @fadd_f16_imm_b(
 ; GFX11-NEXT:    s_mov_b32 s3, s7
 ; GFX11-NEXT:    buffer_load_u16 v0, off, s[0:3], 0
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_f16_e32 v0, 2.0, v0
+; GFX11-NEXT:    v_mov_b16_e32 v0.h, 0x4000
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_add_f16_e32 v0.l, v0.l, v0.h
 ; GFX11-NEXT:    buffer_store_b16 v0, off, s[4:7], 0
 ; GFX11-NEXT:    s_nop 0
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)