[llvm] [RISCV] Use vwsll.vi/vx + vwadd.wv to lower vector.interleave when Zvbb enabled. (PR #67521)

[Luke Lau via llvm-commits]

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@@ -641,6 +641,24 @@ foreach vtiToWti = AllWidenableIntVectors in {
               (!cast<Instruction>("PseudoVWSLL_VI_"#vti.LMul.MX#"_MASK")
                  wti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$rs1,
                  (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
+
+    def : Pat<(riscv_vwsll_vl
+                 (vti.Vector vti.RegClass:$rs2),
+                 (vti.Vector (Low8BitsSplatPat (XLenVT GPR:$rs1))),
+                 (wti.Vector wti.RegClass:$merge),
+                 (vti.Mask V0), VLOpFrag),
+              (!cast<Instruction>("PseudoVWSLL_VX_"#vti.LMul.MX#"_MASK")
+                 wti.RegClass:$merge, vti.RegClass:$rs2, GPR:$rs1,
+                 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
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lukel97 wrote:

Should there be a _VV pattern too for completeness sake?

https://github.com/llvm/llvm-project/pull/67521