[PATCH] D151311: [ScheduleDAG] Fix error assert target

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG13c603a41f13: [ScheduleDAG] Fix false assert target (authored by clearlov7e77, committed by laichunfeng <laichunfeng at tencent.com>).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151311/new/

https://reviews.llvm.org/D151311

Files:
  llvm/lib/CodeGen/ScheduleDAG.cpp


Index: llvm/lib/CodeGen/ScheduleDAG.cpp
===================================================================
--- llvm/lib/CodeGen/ScheduleDAG.cpp
+++ llvm/lib/CodeGen/ScheduleDAG.cpp
@@ -201,7 +201,7 @@
   }
   if (!isScheduled) {
     if (D.isWeak()) {
-      assert(WeakSuccsLeft > 0 && "WeakSuccsLeft will underflow!");
+      assert(N->WeakSuccsLeft > 0 && "WeakSuccsLeft will underflow!");
       --N->WeakSuccsLeft;
     } else {
       assert(N->NumSuccsLeft > 0 && "NumSuccsLeft will underflow!");


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