[llvm] [RISCV] Use vwsll.vi/vx + vwadd.wv to lower vector.interleave when Zvbb enabled. (PR #67521)
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Wed Sep 27 00:34:40 PDT 2023
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git-clang-format --diff 77813b088eb714ecb888c6804b265523fa254eb7 3f0aa02bb54b232dcec25f21dd52b735cd33f276 -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVISelLowering.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 2675b0ce43e4..08ed0b221853 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -125,7 +125,8 @@ enum NodeType : unsigned {
FPCLASS,
// Floating point fmax and fmin matching the RISC-V instruction semantics.
- FMAX, FMIN,
+ FMAX,
+ FMIN,
// READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
// (returns (Lo, Hi)). It takes a chain operand.
@@ -138,10 +139,17 @@ enum NodeType : unsigned {
UNZIP,
// Scalar cryptography
- CLMUL, CLMULH, CLMULR,
- SHA256SIG0, SHA256SIG1, SHA256SUM0, SHA256SUM1,
- SM4KS, SM4ED,
- SM3P0, SM3P1,
+ CLMUL,
+ CLMULH,
+ CLMULR,
+ SHA256SIG0,
+ SHA256SIG1,
+ SHA256SUM0,
+ SHA256SUM1,
+ SM4KS,
+ SM4ED,
+ SM3P0,
+ SM3P1,
// Vector Extension
FIRST_VL_VECTOR_OP,
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https://github.com/llvm/llvm-project/pull/67521
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