================ @@ -416,12 +416,11 @@ class VRegList<list<dag> LIn, int start, int nf, int lmul, bit isV0> { } // Vector registers -foreach Index = 0-31 in { +foreach Index = !range(0, 32, 1) in { ---------------- topperc wrote: Why is this better? https://github.com/llvm/llvm-project/pull/66494