[llvm] [AArch64] update "rm" inline asm test (PR #67472)

[Nick Desaulniers via llvm-commits]

nickdesaulniers wrote:

> The problem here is that it need to be `ldr x0, [x0]` to be valid?

Yes.

These are the relevant sections of the Arm ARM:
C6.2.166 LDR (immediate)
C6.2.167 LDR (literal)
C6.2.168 LDR (register)

In the immediate and register addressing modes, the second operand must be a memory location. (register example):

`LDR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]`

(immediate has pre and post incrementing modes, and another with an unsigned offset)

There are no addressing modes where the second operand can be a register.

https://github.com/llvm/llvm-project/pull/67472