[llvm] [RISCV] Promote SETCC and VP_SETCC of f16 vectors when only have zvfhmin (PR #66866)

[Michael Maitland via llvm-commits]

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@@ -603,6 +609,31 @@ void VectorLegalizer::PromoteReduction(SDNode *Node,
   Results.push_back(Res);
 }
 
+void VectorLegalizer::PromoteSETCC(SDNode *Node,
+                                   SmallVectorImpl<SDValue> &Results) {
+  MVT VecVT = Node->getOperand(0).getSimpleValueType();
+  MVT NewVecVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VecVT);
+
+  unsigned ExtOp = VecVT.isFloatingPoint() ? ISD::FP_EXTEND : ISD::ANY_EXTEND;
+
+  SDLoc DL(Node);
+  SmallVector<SDValue, 4> Operands(Node->getNumOperands());
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michaelmaitland wrote:

Should this be `SmallVector<SDValue, 5>` so all elements can be inlined if its a `VP_SETCC`?

https://github.com/llvm/llvm-project/pull/66866