[llvm] b26157e - [RISCV] Correct Zhinx load/store patterns to use AddrRegImm.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 26 11:55:19 PDT 2023
Author: Craig Topper
Date: 2023-09-26T11:54:59-07:00
New Revision: b26157edf08184f2620b3df95048a97a1658c021
URL: https://github.com/llvm/llvm-project/commit/b26157edf08184f2620b3df95048a97a1658c021
DIFF: https://github.com/llvm/llvm-project/commit/b26157edf08184f2620b3df95048a97a1658c021.diff
LOG: [RISCV] Correct Zhinx load/store patterns to use AddrRegImm.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
llvm/test/CodeGen/RISCV/half-intrinsics.ll
llvm/test/CodeGen/RISCV/half-mem.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index 810775a782412d4..f2dc2200fea3887 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -425,11 +425,13 @@ def : StPat<store, FSH, FPR16, f16>;
let Predicates = [HasStdExtZhinxOrZhinxmin] in {
/// Loads
-def : Pat<(f16 (load GPR:$rs1)), (COPY_TO_REGCLASS (LH GPR:$rs1, 0), GPRF16)>;
+def : Pat<(f16 (load (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
+ (COPY_TO_REGCLASS (LH GPR:$rs1, simm12:$imm12), GPRF16)>;
/// Stores
-def : Pat<(store (f16 FPR16INX:$rs2), GPR:$rs1),
- (SH (COPY_TO_REGCLASS FPR16INX:$rs2, GPR), GPR:$rs1, 0)>;
+def : Pat<(store (f16 FPR16INX:$rs2),
+ (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)),
+ (SH (COPY_TO_REGCLASS FPR16INX:$rs2, GPR), GPR:$rs1, simm12:$imm12)>;
} // Predicates = [HasStdExtZhinxOrZhinxmin]
let Predicates = [HasStdExtZfhOrZfhmin] in {
diff --git a/llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll b/llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
index 37a59a60780699d..e667325db3aa787 100644
--- a/llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
+++ b/llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
@@ -270,101 +270,57 @@ define half @caller_half_32(<32 x half> %A) nounwind {
; ZHINX32-NEXT: sw s9, 68(sp) # 4-byte Folded Spill
; ZHINX32-NEXT: sw s10, 64(sp) # 4-byte Folded Spill
; ZHINX32-NEXT: sw s11, 60(sp) # 4-byte Folded Spill
-; ZHINX32-NEXT: addi t0, sp, 112
-; ZHINX32-NEXT: lh t0, 0(t0)
+; ZHINX32-NEXT: lh t0, 112(sp)
; ZHINX32-NEXT: sw t0, 56(sp) # 4-byte Folded Spill
-; ZHINX32-NEXT: addi t0, sp, 116
-; ZHINX32-NEXT: lh t0, 0(t0)
+; ZHINX32-NEXT: lh t0, 116(sp)
; ZHINX32-NEXT: sw t0, 52(sp) # 4-byte Folded Spill
-; ZHINX32-NEXT: addi t0, sp, 120
-; ZHINX32-NEXT: lh t0, 0(t0)
+; ZHINX32-NEXT: lh t0, 120(sp)
; ZHINX32-NEXT: sw t0, 48(sp) # 4-byte Folded Spill
-; ZHINX32-NEXT: addi t0, sp, 124
-; ZHINX32-NEXT: lh t0, 0(t0)
+; ZHINX32-NEXT: lh t0, 124(sp)
; ZHINX32-NEXT: sw t0, 44(sp) # 4-byte Folded Spill
-; ZHINX32-NEXT: addi t0, sp, 128
-; ZHINX32-NEXT: lh t0, 0(t0)
-; ZHINX32-NEXT: sw t0, 40(sp) # 4-byte Folded Spill
-; ZHINX32-NEXT: addi t0, sp, 132
-; ZHINX32-NEXT: lh t6, 0(t0)
-; ZHINX32-NEXT: addi t1, sp, 136
-; ZHINX32-NEXT: lh t1, 0(t1)
-; ZHINX32-NEXT: addi s0, sp, 140
-; ZHINX32-NEXT: lh s0, 0(s0)
-; ZHINX32-NEXT: addi s1, sp, 144
-; ZHINX32-NEXT: lh s1, 0(s1)
-; ZHINX32-NEXT: addi s2, sp, 148
-; ZHINX32-NEXT: lh s2, 0(s2)
-; ZHINX32-NEXT: addi s3, sp, 152
-; ZHINX32-NEXT: lh s3, 0(s3)
-; ZHINX32-NEXT: addi s4, sp, 156
-; ZHINX32-NEXT: lh s4, 0(s4)
-; ZHINX32-NEXT: addi s5, sp, 160
-; ZHINX32-NEXT: lh s5, 0(s5)
-; ZHINX32-NEXT: addi s6, sp, 164
-; ZHINX32-NEXT: lh s6, 0(s6)
-; ZHINX32-NEXT: addi s7, sp, 168
-; ZHINX32-NEXT: lh s7, 0(s7)
-; ZHINX32-NEXT: addi s8, sp, 172
-; ZHINX32-NEXT: lh s8, 0(s8)
-; ZHINX32-NEXT: addi s9, sp, 176
-; ZHINX32-NEXT: lh s9, 0(s9)
-; ZHINX32-NEXT: addi s10, sp, 180
-; ZHINX32-NEXT: lh s10, 0(s10)
-; ZHINX32-NEXT: addi s11, sp, 184
-; ZHINX32-NEXT: lh s11, 0(s11)
-; ZHINX32-NEXT: addi ra, sp, 188
-; ZHINX32-NEXT: lh ra, 0(ra)
-; ZHINX32-NEXT: addi t0, sp, 192
-; ZHINX32-NEXT: lh t0, 0(t0)
-; ZHINX32-NEXT: addi t2, sp, 196
-; ZHINX32-NEXT: lh t2, 0(t2)
-; ZHINX32-NEXT: addi t3, sp, 200
-; ZHINX32-NEXT: lh t3, 0(t3)
-; ZHINX32-NEXT: addi t4, sp, 204
-; ZHINX32-NEXT: lh t4, 0(t4)
-; ZHINX32-NEXT: addi t5, sp, 36
-; ZHINX32-NEXT: sh t4, 0(t5)
-; ZHINX32-NEXT: addi t4, sp, 34
-; ZHINX32-NEXT: sh t3, 0(t4)
-; ZHINX32-NEXT: addi t3, sp, 32
-; ZHINX32-NEXT: sh t2, 0(t3)
-; ZHINX32-NEXT: addi t2, sp, 30
-; ZHINX32-NEXT: sh t0, 0(t2)
-; ZHINX32-NEXT: addi t0, sp, 28
-; ZHINX32-NEXT: sh ra, 0(t0)
-; ZHINX32-NEXT: addi t0, sp, 26
-; ZHINX32-NEXT: sh s11, 0(t0)
-; ZHINX32-NEXT: addi t0, sp, 24
-; ZHINX32-NEXT: sh s10, 0(t0)
-; ZHINX32-NEXT: addi t0, sp, 22
-; ZHINX32-NEXT: sh s9, 0(t0)
-; ZHINX32-NEXT: addi t0, sp, 20
-; ZHINX32-NEXT: sh s8, 0(t0)
-; ZHINX32-NEXT: addi t0, sp, 18
-; ZHINX32-NEXT: sh s7, 0(t0)
-; ZHINX32-NEXT: addi t0, sp, 16
-; ZHINX32-NEXT: sh s6, 0(t0)
-; ZHINX32-NEXT: addi t0, sp, 14
-; ZHINX32-NEXT: sh s5, 0(t0)
-; ZHINX32-NEXT: addi t0, sp, 12
-; ZHINX32-NEXT: sh s4, 0(t0)
-; ZHINX32-NEXT: addi t0, sp, 10
-; ZHINX32-NEXT: sh s3, 0(t0)
-; ZHINX32-NEXT: addi t0, sp, 8
-; ZHINX32-NEXT: sh s2, 0(t0)
-; ZHINX32-NEXT: addi t0, sp, 6
-; ZHINX32-NEXT: sh s1, 0(t0)
-; ZHINX32-NEXT: addi t0, sp, 4
-; ZHINX32-NEXT: sh s0, 0(t0)
-; ZHINX32-NEXT: addi t0, sp, 2
-; ZHINX32-NEXT: sh t1, 0(t0)
-; ZHINX32-NEXT: sh t6, 0(sp)
+; ZHINX32-NEXT: lh t6, 128(sp)
+; ZHINX32-NEXT: lh t5, 132(sp)
+; ZHINX32-NEXT: lh t4, 136(sp)
+; ZHINX32-NEXT: lh s0, 140(sp)
+; ZHINX32-NEXT: lh s1, 144(sp)
+; ZHINX32-NEXT: lh s2, 148(sp)
+; ZHINX32-NEXT: lh s3, 152(sp)
+; ZHINX32-NEXT: lh s4, 156(sp)
+; ZHINX32-NEXT: lh s5, 160(sp)
+; ZHINX32-NEXT: lh s6, 164(sp)
+; ZHINX32-NEXT: lh s7, 168(sp)
+; ZHINX32-NEXT: lh s8, 172(sp)
+; ZHINX32-NEXT: lh s9, 176(sp)
+; ZHINX32-NEXT: lh s10, 180(sp)
+; ZHINX32-NEXT: lh s11, 184(sp)
+; ZHINX32-NEXT: lh ra, 188(sp)
+; ZHINX32-NEXT: lh t3, 192(sp)
+; ZHINX32-NEXT: lh t2, 196(sp)
+; ZHINX32-NEXT: lh t1, 200(sp)
+; ZHINX32-NEXT: lh t0, 204(sp)
+; ZHINX32-NEXT: sh t0, 36(sp)
+; ZHINX32-NEXT: sh t1, 34(sp)
+; ZHINX32-NEXT: sh t2, 32(sp)
+; ZHINX32-NEXT: sh t3, 30(sp)
+; ZHINX32-NEXT: sh ra, 28(sp)
+; ZHINX32-NEXT: sh s11, 26(sp)
+; ZHINX32-NEXT: sh s10, 24(sp)
+; ZHINX32-NEXT: sh s9, 22(sp)
+; ZHINX32-NEXT: sh s8, 20(sp)
+; ZHINX32-NEXT: sh s7, 18(sp)
+; ZHINX32-NEXT: sh s6, 16(sp)
+; ZHINX32-NEXT: sh s5, 14(sp)
+; ZHINX32-NEXT: sh s4, 12(sp)
+; ZHINX32-NEXT: sh s3, 10(sp)
+; ZHINX32-NEXT: sh s2, 8(sp)
+; ZHINX32-NEXT: sh s1, 6(sp)
+; ZHINX32-NEXT: sh s0, 4(sp)
+; ZHINX32-NEXT: sh t4, 2(sp)
+; ZHINX32-NEXT: sh t5, 0(sp)
; ZHINX32-NEXT: lw t2, 56(sp) # 4-byte Folded Reload
; ZHINX32-NEXT: lw t3, 52(sp) # 4-byte Folded Reload
; ZHINX32-NEXT: lw t4, 48(sp) # 4-byte Folded Reload
; ZHINX32-NEXT: lw t5, 44(sp) # 4-byte Folded Reload
-; ZHINX32-NEXT: lw t6, 40(sp) # 4-byte Folded Reload
; ZHINX32-NEXT: call callee_half_32 at plt
; ZHINX32-NEXT: lw ra, 108(sp) # 4-byte Folded Reload
; ZHINX32-NEXT: lw s0, 104(sp) # 4-byte Folded Reload
@@ -384,130 +340,86 @@ define half @caller_half_32(<32 x half> %A) nounwind {
;
; ZHINX64-LABEL: caller_half_32:
; ZHINX64: # %bb.0:
-; ZHINX64-NEXT: addi sp, sp, -192
-; ZHINX64-NEXT: sd ra, 184(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: sd s0, 176(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: sd s1, 168(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: sd s2, 160(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: sd s3, 152(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: sd s4, 144(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: sd s5, 136(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: sd s6, 128(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: sd s7, 120(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: sd s8, 112(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: sd s9, 104(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: sd s10, 96(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: sd s11, 88(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: addi t0, sp, 192
-; ZHINX64-NEXT: lh t0, 0(t0)
-; ZHINX64-NEXT: sd t0, 80(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: addi t0, sp, 200
-; ZHINX64-NEXT: lh t0, 0(t0)
-; ZHINX64-NEXT: sd t0, 72(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: addi t0, sp, 208
-; ZHINX64-NEXT: lh t0, 0(t0)
+; ZHINX64-NEXT: addi sp, sp, -176
+; ZHINX64-NEXT: sd ra, 168(sp) # 8-byte Folded Spill
+; ZHINX64-NEXT: sd s0, 160(sp) # 8-byte Folded Spill
+; ZHINX64-NEXT: sd s1, 152(sp) # 8-byte Folded Spill
+; ZHINX64-NEXT: sd s2, 144(sp) # 8-byte Folded Spill
+; ZHINX64-NEXT: sd s3, 136(sp) # 8-byte Folded Spill
+; ZHINX64-NEXT: sd s4, 128(sp) # 8-byte Folded Spill
+; ZHINX64-NEXT: sd s5, 120(sp) # 8-byte Folded Spill
+; ZHINX64-NEXT: sd s6, 112(sp) # 8-byte Folded Spill
+; ZHINX64-NEXT: sd s7, 104(sp) # 8-byte Folded Spill
+; ZHINX64-NEXT: sd s8, 96(sp) # 8-byte Folded Spill
+; ZHINX64-NEXT: sd s9, 88(sp) # 8-byte Folded Spill
+; ZHINX64-NEXT: sd s10, 80(sp) # 8-byte Folded Spill
+; ZHINX64-NEXT: sd s11, 72(sp) # 8-byte Folded Spill
+; ZHINX64-NEXT: lh t0, 176(sp)
; ZHINX64-NEXT: sd t0, 64(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: addi t0, sp, 216
-; ZHINX64-NEXT: lh t0, 0(t0)
+; ZHINX64-NEXT: lh t0, 184(sp)
; ZHINX64-NEXT: sd t0, 56(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: addi t0, sp, 224
-; ZHINX64-NEXT: lh t0, 0(t0)
+; ZHINX64-NEXT: lh t0, 192(sp)
; ZHINX64-NEXT: sd t0, 48(sp) # 8-byte Folded Spill
-; ZHINX64-NEXT: addi t0, sp, 232
-; ZHINX64-NEXT: lh t6, 0(t0)
-; ZHINX64-NEXT: addi t1, sp, 240
-; ZHINX64-NEXT: lh t1, 0(t1)
-; ZHINX64-NEXT: addi s0, sp, 248
-; ZHINX64-NEXT: lh s0, 0(s0)
-; ZHINX64-NEXT: addi s1, sp, 256
-; ZHINX64-NEXT: lh s1, 0(s1)
-; ZHINX64-NEXT: addi s2, sp, 264
-; ZHINX64-NEXT: lh s2, 0(s2)
-; ZHINX64-NEXT: addi s3, sp, 272
-; ZHINX64-NEXT: lh s3, 0(s3)
-; ZHINX64-NEXT: addi s4, sp, 280
-; ZHINX64-NEXT: lh s4, 0(s4)
-; ZHINX64-NEXT: addi s5, sp, 288
-; ZHINX64-NEXT: lh s5, 0(s5)
-; ZHINX64-NEXT: addi s6, sp, 296
-; ZHINX64-NEXT: lh s6, 0(s6)
-; ZHINX64-NEXT: addi s7, sp, 304
-; ZHINX64-NEXT: lh s7, 0(s7)
-; ZHINX64-NEXT: addi s8, sp, 312
-; ZHINX64-NEXT: lh s8, 0(s8)
-; ZHINX64-NEXT: addi s9, sp, 320
-; ZHINX64-NEXT: lh s9, 0(s9)
-; ZHINX64-NEXT: addi s10, sp, 328
-; ZHINX64-NEXT: lh s10, 0(s10)
-; ZHINX64-NEXT: addi s11, sp, 336
-; ZHINX64-NEXT: lh s11, 0(s11)
-; ZHINX64-NEXT: addi ra, sp, 344
-; ZHINX64-NEXT: lh ra, 0(ra)
-; ZHINX64-NEXT: addi t0, sp, 352
-; ZHINX64-NEXT: lh t0, 0(t0)
-; ZHINX64-NEXT: addi t2, sp, 360
-; ZHINX64-NEXT: lh t2, 0(t2)
-; ZHINX64-NEXT: addi t3, sp, 368
-; ZHINX64-NEXT: lh t3, 0(t3)
-; ZHINX64-NEXT: addi t4, sp, 376
-; ZHINX64-NEXT: lh t4, 0(t4)
-; ZHINX64-NEXT: addi t5, sp, 36
-; ZHINX64-NEXT: sh t4, 0(t5)
-; ZHINX64-NEXT: addi t4, sp, 34
-; ZHINX64-NEXT: sh t3, 0(t4)
-; ZHINX64-NEXT: addi t3, sp, 32
-; ZHINX64-NEXT: sh t2, 0(t3)
-; ZHINX64-NEXT: addi t2, sp, 30
-; ZHINX64-NEXT: sh t0, 0(t2)
-; ZHINX64-NEXT: addi t0, sp, 28
-; ZHINX64-NEXT: sh ra, 0(t0)
-; ZHINX64-NEXT: addi t0, sp, 26
-; ZHINX64-NEXT: sh s11, 0(t0)
-; ZHINX64-NEXT: addi t0, sp, 24
-; ZHINX64-NEXT: sh s10, 0(t0)
-; ZHINX64-NEXT: addi t0, sp, 22
-; ZHINX64-NEXT: sh s9, 0(t0)
-; ZHINX64-NEXT: addi t0, sp, 20
-; ZHINX64-NEXT: sh s8, 0(t0)
-; ZHINX64-NEXT: addi t0, sp, 18
-; ZHINX64-NEXT: sh s7, 0(t0)
-; ZHINX64-NEXT: addi t0, sp, 16
-; ZHINX64-NEXT: sh s6, 0(t0)
-; ZHINX64-NEXT: addi t0, sp, 14
-; ZHINX64-NEXT: sh s5, 0(t0)
-; ZHINX64-NEXT: addi t0, sp, 12
-; ZHINX64-NEXT: sh s4, 0(t0)
-; ZHINX64-NEXT: addi t0, sp, 10
-; ZHINX64-NEXT: sh s3, 0(t0)
-; ZHINX64-NEXT: addi t0, sp, 8
-; ZHINX64-NEXT: sh s2, 0(t0)
-; ZHINX64-NEXT: addi t0, sp, 6
-; ZHINX64-NEXT: sh s1, 0(t0)
-; ZHINX64-NEXT: addi t0, sp, 4
-; ZHINX64-NEXT: sh s0, 0(t0)
-; ZHINX64-NEXT: addi t0, sp, 2
-; ZHINX64-NEXT: sh t1, 0(t0)
-; ZHINX64-NEXT: sh t6, 0(sp)
-; ZHINX64-NEXT: ld t2, 80(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld t3, 72(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld t4, 64(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld t5, 56(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld t6, 48(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: lh t0, 200(sp)
+; ZHINX64-NEXT: sd t0, 40(sp) # 8-byte Folded Spill
+; ZHINX64-NEXT: lh t6, 208(sp)
+; ZHINX64-NEXT: lh t5, 216(sp)
+; ZHINX64-NEXT: lh t4, 224(sp)
+; ZHINX64-NEXT: lh s0, 232(sp)
+; ZHINX64-NEXT: lh s1, 240(sp)
+; ZHINX64-NEXT: lh s2, 248(sp)
+; ZHINX64-NEXT: lh s3, 256(sp)
+; ZHINX64-NEXT: lh s4, 264(sp)
+; ZHINX64-NEXT: lh s5, 272(sp)
+; ZHINX64-NEXT: lh s6, 280(sp)
+; ZHINX64-NEXT: lh s7, 288(sp)
+; ZHINX64-NEXT: lh s8, 296(sp)
+; ZHINX64-NEXT: lh s9, 304(sp)
+; ZHINX64-NEXT: lh s10, 312(sp)
+; ZHINX64-NEXT: lh s11, 320(sp)
+; ZHINX64-NEXT: lh ra, 328(sp)
+; ZHINX64-NEXT: lh t3, 336(sp)
+; ZHINX64-NEXT: lh t2, 344(sp)
+; ZHINX64-NEXT: lh t1, 352(sp)
+; ZHINX64-NEXT: lh t0, 360(sp)
+; ZHINX64-NEXT: sh t0, 36(sp)
+; ZHINX64-NEXT: sh t1, 34(sp)
+; ZHINX64-NEXT: sh t2, 32(sp)
+; ZHINX64-NEXT: sh t3, 30(sp)
+; ZHINX64-NEXT: sh ra, 28(sp)
+; ZHINX64-NEXT: sh s11, 26(sp)
+; ZHINX64-NEXT: sh s10, 24(sp)
+; ZHINX64-NEXT: sh s9, 22(sp)
+; ZHINX64-NEXT: sh s8, 20(sp)
+; ZHINX64-NEXT: sh s7, 18(sp)
+; ZHINX64-NEXT: sh s6, 16(sp)
+; ZHINX64-NEXT: sh s5, 14(sp)
+; ZHINX64-NEXT: sh s4, 12(sp)
+; ZHINX64-NEXT: sh s3, 10(sp)
+; ZHINX64-NEXT: sh s2, 8(sp)
+; ZHINX64-NEXT: sh s1, 6(sp)
+; ZHINX64-NEXT: sh s0, 4(sp)
+; ZHINX64-NEXT: sh t4, 2(sp)
+; ZHINX64-NEXT: sh t5, 0(sp)
+; ZHINX64-NEXT: ld t2, 64(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: ld t3, 56(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: ld t4, 48(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: ld t5, 40(sp) # 8-byte Folded Reload
; ZHINX64-NEXT: call callee_half_32 at plt
-; ZHINX64-NEXT: ld ra, 184(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld s0, 176(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld s1, 168(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld s2, 160(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld s3, 152(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld s4, 144(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld s5, 136(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld s6, 128(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld s7, 120(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld s8, 112(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld s9, 104(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld s10, 96(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: ld s11, 88(sp) # 8-byte Folded Reload
-; ZHINX64-NEXT: addi sp, sp, 192
+; ZHINX64-NEXT: ld ra, 168(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: ld s0, 160(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: ld s1, 152(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: ld s2, 144(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: ld s3, 136(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: ld s4, 128(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: ld s5, 120(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: ld s6, 112(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: ld s7, 104(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: ld s8, 96(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: ld s9, 88(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: ld s10, 80(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: ld s11, 72(sp) # 8-byte Folded Reload
+; ZHINX64-NEXT: addi sp, sp, 176
; ZHINX64-NEXT: ret
;
; ZFINX32-LABEL: caller_half_32:
diff --git a/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll b/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
index 60c6473e2b2f68d..db35a55e9f59fc2 100644
--- a/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
+++ b/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
@@ -253,17 +253,15 @@ define half @fcopysign_fneg(half %a, half %b) nounwind {
; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
; RV32IZHINXMIN-NEXT: fneg.s a1, a1
; RV32IZHINXMIN-NEXT: fcvt.h.s a1, a1
-; RV32IZHINXMIN-NEXT: addi a2, sp, 8
-; RV32IZHINXMIN-NEXT: sh a0, 0(a2)
-; RV32IZHINXMIN-NEXT: addi a0, sp, 12
-; RV32IZHINXMIN-NEXT: sh a1, 0(a0)
+; RV32IZHINXMIN-NEXT: sh a0, 8(sp)
+; RV32IZHINXMIN-NEXT: sh a1, 12(sp)
; RV32IZHINXMIN-NEXT: lbu a0, 9(sp)
; RV32IZHINXMIN-NEXT: lbu a1, 13(sp)
; RV32IZHINXMIN-NEXT: andi a0, a0, 127
; RV32IZHINXMIN-NEXT: andi a1, a1, 128
; RV32IZHINXMIN-NEXT: or a0, a0, a1
; RV32IZHINXMIN-NEXT: sb a0, 9(sp)
-; RV32IZHINXMIN-NEXT: lh a0, 0(a2)
+; RV32IZHINXMIN-NEXT: lh a0, 8(sp)
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
; RV32IZHINXMIN-NEXT: ret
;
@@ -273,17 +271,15 @@ define half @fcopysign_fneg(half %a, half %b) nounwind {
; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
; RV64IZHINXMIN-NEXT: fneg.s a1, a1
; RV64IZHINXMIN-NEXT: fcvt.h.s a1, a1
-; RV64IZHINXMIN-NEXT: mv a2, sp
-; RV64IZHINXMIN-NEXT: sh a0, 0(a2)
-; RV64IZHINXMIN-NEXT: addi a0, sp, 8
-; RV64IZHINXMIN-NEXT: sh a1, 0(a0)
+; RV64IZHINXMIN-NEXT: sh a0, 0(sp)
+; RV64IZHINXMIN-NEXT: sh a1, 8(sp)
; RV64IZHINXMIN-NEXT: lbu a0, 1(sp)
; RV64IZHINXMIN-NEXT: lbu a1, 9(sp)
; RV64IZHINXMIN-NEXT: andi a0, a0, 127
; RV64IZHINXMIN-NEXT: andi a1, a1, 128
; RV64IZHINXMIN-NEXT: or a0, a0, a1
; RV64IZHINXMIN-NEXT: sb a0, 1(sp)
-; RV64IZHINXMIN-NEXT: lh a0, 0(a2)
+; RV64IZHINXMIN-NEXT: lh a0, 0(sp)
; RV64IZHINXMIN-NEXT: addi sp, sp, 16
; RV64IZHINXMIN-NEXT: ret
%1 = fneg half %b
diff --git a/llvm/test/CodeGen/RISCV/half-intrinsics.ll b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
index 18003dcb039e32f..2d4b7538c34d135 100644
--- a/llvm/test/CodeGen/RISCV/half-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
@@ -2092,34 +2092,30 @@ define half @copysign_f16(half %a, half %b) nounwind {
; RV32IZHINXMIN-LABEL: copysign_f16:
; RV32IZHINXMIN: # %bb.0:
; RV32IZHINXMIN-NEXT: addi sp, sp, -16
-; RV32IZHINXMIN-NEXT: addi a2, sp, 12
-; RV32IZHINXMIN-NEXT: sh a1, 0(a2)
-; RV32IZHINXMIN-NEXT: addi a1, sp, 8
-; RV32IZHINXMIN-NEXT: sh a0, 0(a1)
+; RV32IZHINXMIN-NEXT: sh a1, 12(sp)
+; RV32IZHINXMIN-NEXT: sh a0, 8(sp)
; RV32IZHINXMIN-NEXT: lbu a0, 13(sp)
-; RV32IZHINXMIN-NEXT: lbu a2, 9(sp)
+; RV32IZHINXMIN-NEXT: lbu a1, 9(sp)
; RV32IZHINXMIN-NEXT: andi a0, a0, 128
-; RV32IZHINXMIN-NEXT: andi a2, a2, 127
-; RV32IZHINXMIN-NEXT: or a0, a2, a0
+; RV32IZHINXMIN-NEXT: andi a1, a1, 127
+; RV32IZHINXMIN-NEXT: or a0, a1, a0
; RV32IZHINXMIN-NEXT: sb a0, 9(sp)
-; RV32IZHINXMIN-NEXT: lh a0, 0(a1)
+; RV32IZHINXMIN-NEXT: lh a0, 8(sp)
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: copysign_f16:
; RV64IZHINXMIN: # %bb.0:
; RV64IZHINXMIN-NEXT: addi sp, sp, -16
-; RV64IZHINXMIN-NEXT: addi a2, sp, 8
-; RV64IZHINXMIN-NEXT: sh a1, 0(a2)
-; RV64IZHINXMIN-NEXT: mv a1, sp
-; RV64IZHINXMIN-NEXT: sh a0, 0(a1)
+; RV64IZHINXMIN-NEXT: sh a1, 8(sp)
+; RV64IZHINXMIN-NEXT: sh a0, 0(sp)
; RV64IZHINXMIN-NEXT: lbu a0, 9(sp)
-; RV64IZHINXMIN-NEXT: lbu a2, 1(sp)
+; RV64IZHINXMIN-NEXT: lbu a1, 1(sp)
; RV64IZHINXMIN-NEXT: andi a0, a0, 128
-; RV64IZHINXMIN-NEXT: andi a2, a2, 127
-; RV64IZHINXMIN-NEXT: or a0, a2, a0
+; RV64IZHINXMIN-NEXT: andi a1, a1, 127
+; RV64IZHINXMIN-NEXT: or a0, a1, a0
; RV64IZHINXMIN-NEXT: sb a0, 1(sp)
-; RV64IZHINXMIN-NEXT: lh a0, 0(a1)
+; RV64IZHINXMIN-NEXT: lh a0, 0(sp)
; RV64IZHINXMIN-NEXT: addi sp, sp, 16
; RV64IZHINXMIN-NEXT: ret
%1 = call half @llvm.copysign.f16(half %a, half %b)
diff --git a/llvm/test/CodeGen/RISCV/half-mem.ll b/llvm/test/CodeGen/RISCV/half-mem.ll
index 35b129dfcdb7858..bb25d2a7443df82 100644
--- a/llvm/test/CodeGen/RISCV/half-mem.ll
+++ b/llvm/test/CodeGen/RISCV/half-mem.ll
@@ -27,8 +27,7 @@ define half @flh(ptr %a) nounwind {
; CHECKIZHINX-LABEL: flh:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: lh a1, 0(a0)
-; CHECKIZHINX-NEXT: addi a0, a0, 6
-; CHECKIZHINX-NEXT: lh a0, 0(a0)
+; CHECKIZHINX-NEXT: lh a0, 6(a0)
; CHECKIZHINX-NEXT: fadd.h a0, a1, a0
; CHECKIZHINX-NEXT: ret
;
@@ -44,12 +43,11 @@ define half @flh(ptr %a) nounwind {
;
; CHECKIZHINXMIN-LABEL: flh:
; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: lh a1, 0(a0)
-; CHECKIZHINXMIN-NEXT: addi a0, a0, 6
+; CHECKIZHINXMIN-NEXT: lh a1, 6(a0)
; CHECKIZHINXMIN-NEXT: lh a0, 0(a0)
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT: fadd.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, a1
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = load half, ptr %a
@@ -75,8 +73,7 @@ define dso_local void @fsh(ptr %a, half %b, half %c) nounwind {
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fadd.h a1, a1, a2
; CHECKIZHINX-NEXT: sh a1, 0(a0)
-; CHECKIZHINX-NEXT: addi a0, a0, 16
-; CHECKIZHINX-NEXT: sh a1, 0(a0)
+; CHECKIZHINX-NEXT: sh a1, 16(a0)
; CHECKIZHINX-NEXT: ret
;
; CHECKIZFHMIN-LABEL: fsh:
@@ -96,8 +93,7 @@ define dso_local void @fsh(ptr %a, half %b, half %c) nounwind {
; CHECKIZHINXMIN-NEXT: fadd.s a1, a1, a2
; CHECKIZHINXMIN-NEXT: fcvt.h.s a1, a1
; CHECKIZHINXMIN-NEXT: sh a1, 0(a0)
-; CHECKIZHINXMIN-NEXT: addi a0, a0, 16
-; CHECKIZHINXMIN-NEXT: sh a1, 0(a0)
+; CHECKIZHINXMIN-NEXT: sh a1, 16(a0)
; CHECKIZHINXMIN-NEXT: ret
%1 = fadd half %b, %c
store half %1, ptr %a
@@ -127,12 +123,11 @@ define half @flh_fsh_global(half %a, half %b) nounwind {
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fadd.h a0, a0, a1
; CHECKIZHINX-NEXT: lui a1, %hi(G)
-; CHECKIZHINX-NEXT: addi a1, a1, %lo(G)
-; CHECKIZHINX-NEXT: lh zero, 0(a1)
-; CHECKIZHINX-NEXT: sh a0, 0(a1)
-; CHECKIZHINX-NEXT: addi a1, a1, 18
-; CHECKIZHINX-NEXT: lh zero, 0(a1)
-; CHECKIZHINX-NEXT: sh a0, 0(a1)
+; CHECKIZHINX-NEXT: lh zero, %lo(G)(a1)
+; CHECKIZHINX-NEXT: addi a2, a1, %lo(G)
+; CHECKIZHINX-NEXT: sh a0, %lo(G)(a1)
+; CHECKIZHINX-NEXT: lh zero, 18(a2)
+; CHECKIZHINX-NEXT: sh a0, 18(a2)
; CHECKIZHINX-NEXT: ret
;
; CHECKIZFHMIN-LABEL: flh_fsh_global:
@@ -156,12 +151,11 @@ define half @flh_fsh_global(half %a, half %b) nounwind {
; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, a1
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: lui a1, %hi(G)
-; CHECKIZHINXMIN-NEXT: addi a1, a1, %lo(G)
-; CHECKIZHINXMIN-NEXT: lh zero, 0(a1)
-; CHECKIZHINXMIN-NEXT: sh a0, 0(a1)
-; CHECKIZHINXMIN-NEXT: addi a1, a1, 18
-; CHECKIZHINXMIN-NEXT: lh zero, 0(a1)
-; CHECKIZHINXMIN-NEXT: sh a0, 0(a1)
+; CHECKIZHINXMIN-NEXT: lh zero, %lo(G)(a1)
+; CHECKIZHINXMIN-NEXT: addi a2, a1, %lo(G)
+; CHECKIZHINXMIN-NEXT: sh a0, %lo(G)(a1)
+; CHECKIZHINXMIN-NEXT: lh zero, 18(a2)
+; CHECKIZHINXMIN-NEXT: sh a0, 18(a2)
; CHECKIZHINXMIN-NEXT: ret
%1 = fadd half %a, %b
%2 = load volatile half, ptr @G
@@ -194,20 +188,18 @@ define half @flh_fsh_constant(half %a) nounwind {
; RV32IZHINX-LABEL: flh_fsh_constant:
; RV32IZHINX: # %bb.0:
; RV32IZHINX-NEXT: lui a1, 912092
-; RV32IZHINX-NEXT: addi a1, a1, -273
-; RV32IZHINX-NEXT: lh a2, 0(a1)
+; RV32IZHINX-NEXT: lh a2, -273(a1)
; RV32IZHINX-NEXT: fadd.h a0, a0, a2
-; RV32IZHINX-NEXT: sh a0, 0(a1)
+; RV32IZHINX-NEXT: sh a0, -273(a1)
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: flh_fsh_constant:
; RV64IZHINX: # %bb.0:
; RV64IZHINX-NEXT: lui a1, 228023
; RV64IZHINX-NEXT: slli a1, a1, 2
-; RV64IZHINX-NEXT: addi a1, a1, -273
-; RV64IZHINX-NEXT: lh a2, 0(a1)
+; RV64IZHINX-NEXT: lh a2, -273(a1)
; RV64IZHINX-NEXT: fadd.h a0, a0, a2
-; RV64IZHINX-NEXT: sh a0, 0(a1)
+; RV64IZHINX-NEXT: sh a0, -273(a1)
; RV64IZHINX-NEXT: ret
;
; RV32IZFHMIN-LABEL: flh_fsh_constant:
@@ -236,26 +228,24 @@ define half @flh_fsh_constant(half %a) nounwind {
; RV32IZHINXMIN-LABEL: flh_fsh_constant:
; RV32IZHINXMIN: # %bb.0:
; RV32IZHINXMIN-NEXT: lui a1, 912092
-; RV32IZHINXMIN-NEXT: addi a1, a1, -273
-; RV32IZHINXMIN-NEXT: lh a2, 0(a1)
+; RV32IZHINXMIN-NEXT: lh a2, -273(a1)
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV32IZHINXMIN-NEXT: fcvt.s.h a2, a2
; RV32IZHINXMIN-NEXT: fadd.s a0, a0, a2
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV32IZHINXMIN-NEXT: sh a0, 0(a1)
+; RV32IZHINXMIN-NEXT: sh a0, -273(a1)
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: flh_fsh_constant:
; RV64IZHINXMIN: # %bb.0:
; RV64IZHINXMIN-NEXT: lui a1, 228023
; RV64IZHINXMIN-NEXT: slli a1, a1, 2
-; RV64IZHINXMIN-NEXT: addi a1, a1, -273
-; RV64IZHINXMIN-NEXT: lh a2, 0(a1)
+; RV64IZHINXMIN-NEXT: lh a2, -273(a1)
; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV64IZHINXMIN-NEXT: fcvt.s.h a2, a2
; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a2
; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV64IZHINXMIN-NEXT: sh a0, 0(a1)
+; RV64IZHINXMIN-NEXT: sh a0, -273(a1)
; RV64IZHINXMIN-NEXT: ret
%1 = inttoptr i32 3735928559 to ptr
%2 = load volatile half, ptr %1
@@ -302,16 +292,13 @@ define half @flh_stack(half %a) nounwind {
; RV32IZHINX-NEXT: addi sp, sp, -16
; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IZHINX-NEXT: mv s0, a0
-; RV32IZHINX-NEXT: mv a0, sp
-; RV32IZHINX-NEXT: mv s1, sp
+; RV32IZHINX-NEXT: addi a0, sp, 4
; RV32IZHINX-NEXT: call notdead at plt
-; RV32IZHINX-NEXT: lh a0, 0(s1)
+; RV32IZHINX-NEXT: lh a0, 4(sp)
; RV32IZHINX-NEXT: fadd.h a0, a0, s0
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32IZHINX-NEXT: addi sp, sp, 16
; RV32IZHINX-NEXT: ret
;
@@ -320,16 +307,13 @@ define half @flh_stack(half %a) nounwind {
; RV64IZHINX-NEXT: addi sp, sp, -32
; RV64IZHINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IZHINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64IZHINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64IZHINX-NEXT: mv s0, a0
-; RV64IZHINX-NEXT: addi a0, sp, 4
-; RV64IZHINX-NEXT: addi s1, sp, 4
+; RV64IZHINX-NEXT: addi a0, sp, 12
; RV64IZHINX-NEXT: call notdead at plt
-; RV64IZHINX-NEXT: lh a0, 0(s1)
+; RV64IZHINX-NEXT: lh a0, 12(sp)
; RV64IZHINX-NEXT: fadd.h a0, a0, s0
; RV64IZHINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IZHINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64IZHINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64IZHINX-NEXT: addi sp, sp, 32
; RV64IZHINX-NEXT: ret
;
@@ -374,19 +358,16 @@ define half @flh_stack(half %a) nounwind {
; RV32IZHINXMIN-NEXT: addi sp, sp, -16
; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IZHINXMIN-NEXT: mv s0, a0
-; RV32IZHINXMIN-NEXT: mv a0, sp
-; RV32IZHINXMIN-NEXT: mv s1, sp
+; RV32IZHINXMIN-NEXT: addi a0, sp, 4
; RV32IZHINXMIN-NEXT: call notdead at plt
-; RV32IZHINXMIN-NEXT: lh a0, 0(s1)
+; RV32IZHINXMIN-NEXT: lh a0, 4(sp)
; RV32IZHINXMIN-NEXT: fcvt.s.h a1, s0
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV32IZHINXMIN-NEXT: fadd.s a0, a0, a1
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
; RV32IZHINXMIN-NEXT: ret
;
@@ -395,19 +376,16 @@ define half @flh_stack(half %a) nounwind {
; RV64IZHINXMIN-NEXT: addi sp, sp, -32
; RV64IZHINXMIN-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IZHINXMIN-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64IZHINXMIN-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64IZHINXMIN-NEXT: mv s0, a0
-; RV64IZHINXMIN-NEXT: addi a0, sp, 4
-; RV64IZHINXMIN-NEXT: addi s1, sp, 4
+; RV64IZHINXMIN-NEXT: addi a0, sp, 12
; RV64IZHINXMIN-NEXT: call notdead at plt
-; RV64IZHINXMIN-NEXT: lh a0, 0(s1)
+; RV64IZHINXMIN-NEXT: lh a0, 12(sp)
; RV64IZHINXMIN-NEXT: fcvt.s.h a1, s0
; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1
; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV64IZHINXMIN-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IZHINXMIN-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64IZHINXMIN-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64IZHINXMIN-NEXT: addi sp, sp, 32
; RV64IZHINXMIN-NEXT: ret
%1 = alloca half, align 4
@@ -447,8 +425,7 @@ define dso_local void @fsh_stack(half %a, half %b) nounwind {
; RV32IZHINX-NEXT: addi sp, sp, -16
; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZHINX-NEXT: fadd.h a0, a0, a1
-; RV32IZHINX-NEXT: addi a1, sp, 8
-; RV32IZHINX-NEXT: sh a0, 0(a1)
+; RV32IZHINX-NEXT: sh a0, 8(sp)
; RV32IZHINX-NEXT: addi a0, sp, 8
; RV32IZHINX-NEXT: call notdead at plt
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -460,8 +437,7 @@ define dso_local void @fsh_stack(half %a, half %b) nounwind {
; RV64IZHINX-NEXT: addi sp, sp, -16
; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZHINX-NEXT: fadd.h a0, a0, a1
-; RV64IZHINX-NEXT: addi a1, sp, 4
-; RV64IZHINX-NEXT: sh a0, 0(a1)
+; RV64IZHINX-NEXT: sh a0, 4(sp)
; RV64IZHINX-NEXT: addi a0, sp, 4
; RV64IZHINX-NEXT: call notdead at plt
; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -506,8 +482,7 @@ define dso_local void @fsh_stack(half %a, half %b) nounwind {
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV32IZHINXMIN-NEXT: fadd.s a0, a0, a1
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV32IZHINXMIN-NEXT: addi a1, sp, 8
-; RV32IZHINXMIN-NEXT: sh a0, 0(a1)
+; RV32IZHINXMIN-NEXT: sh a0, 8(sp)
; RV32IZHINXMIN-NEXT: addi a0, sp, 8
; RV32IZHINXMIN-NEXT: call notdead at plt
; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -522,8 +497,7 @@ define dso_local void @fsh_stack(half %a, half %b) nounwind {
; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1
; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV64IZHINXMIN-NEXT: addi a1, sp, 4
-; RV64IZHINXMIN-NEXT: sh a0, 0(a1)
+; RV64IZHINXMIN-NEXT: sh a0, 4(sp)
; RV64IZHINXMIN-NEXT: addi a0, sp, 4
; RV64IZHINXMIN-NEXT: call notdead at plt
; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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