[llvm] [AMDGPU] Src1 of VOP3 DPP instructions can be SGPR on supported subtargets (PR #67461)

[Joe Nash via llvm-commits]

https://github.com/Sisyph commented:

Please add a disassembler test. It might be permissible to accept sgpr as src1 on gfx11 as well as gfx1150 (i.e. disassembler is not strict), but we should at least ensure it is acceptable on gfx1150.

https://github.com/llvm/llvm-project/pull/67461