[llvm] [AMDGPU] Src1 of VOP3 DPP instructions can be SGPR on supported subtargets (PR #67461)

[via llvm-commits]

github-actions[bot] wrote:


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git-clang-format --diff 64b1fbb3bd03531749792bfb20526c0a0dc07838 bec805c74e4b1098fa47aa10c9e66d03701710a2 -- llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp llvm/lib/Target/AMDGPU/GCNSubtarget.h llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index c73cf6b2b..e7d46c0df 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -917,9 +917,7 @@ public:
     return HasDPALU_DPP;
   }
 
-  bool hasDPPSrc1SGPR() const {
-    return HasDPPSrc1SGPR;
-  }
+  bool hasDPPSrc1SGPR() const { return HasDPPSrc1SGPR; }
 
   bool hasPackedFP32Ops() const {
     return HasPackedFP32Ops;

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https://github.com/llvm/llvm-project/pull/67461