[llvm] [NVPTX] Optimize v16i8 reductions (PR #67322)

[Pierre-Andre Saulais via llvm-commits]

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@@ -5294,6 +5295,98 @@ static SDValue PerformEXTRACTCombine(SDNode *N,
   return Result;
 }
 
+static SDValue PerformLOADCombine(SDNode *N,
+                                  TargetLowering::DAGCombinerInfo &DCI) {
+  SelectionDAG &DAG = DCI.DAG;
+  LoadSDNode *LD = cast<LoadSDNode>(N);
+
+  // Lower a v16i8 load into a LoadV4 operation with i32 results instead of
+  // letting ReplaceLoadVector split it into smaller loads during legalization.
+  // This is done at dag-combine1 time, so that vector operations with i8
+  // elements can be optimised away instead of being needlessly split during
+  // legalization, which involves storing to the stack and loading it back.
+  EVT VT = N->getValueType(0);
+  if (VT != MVT::v16i8)
+    return SDValue();
+
+  SDLoc DL(N);
+
+  // Create a v4i32 vector load operation, effectively <4 x v4i8>.
+  unsigned Opc = NVPTXISD::LoadV4;
+  EVT NewVT = MVT::v4i32;
+  EVT EleVT = NewVT.getVectorElementType();
+  unsigned NumEles = NewVT.getVectorNumElements();
+  EVT RetVTs[] = {EleVT, EleVT, EleVT, EleVT, MVT::Other};
+  SDVTList RetVTList = DAG.getVTList(RetVTs);
+  SmallVector<SDValue, 8> Ops(N->op_begin(), N->op_end());
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pasaulais wrote:

Good point, that's a simpler way of doing this.

https://github.com/llvm/llvm-project/pull/67322