[llvm] 733e3c6 - [RISCV] Update comment on -w stripping pass. NFC (#67415)

[via llvm-commits]

Author: Luke Lau
Date: 2023-09-26T16:48:34+01:00
New Revision: 733e3c60a437215a2a75f8a6a0df6ff4a61778cf

URL: https://github.com/llvm/llvm-project/commit/733e3c60a437215a2a75f8a6a0df6ff4a61778cf
DIFF: https://github.com/llvm/llvm-project/commit/733e3c60a437215a2a75f8a6a0df6ff4a61778cf.diff

LOG: [RISCV] Update comment on -w stripping pass. NFC (#67415)

It looks like we only strip the -w suffix from addw and not addiw
(because c.addiw and c.addi have the same register encoding), but the
comment in the header seems to have it the other way round.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index bd294c669735f4f..3c608bf8b50b57d 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -12,10 +12,11 @@
 // extended bits aren't consumed or because the input was already sign extended
 // by an earlier instruction.
 //
-// Then it removes the -w suffix from each addiw and slliw instructions
+// Then it removes the -w suffix from addw, slliw and mulw instructions
 // whenever all users are dependent only on the lower word of the result of the
-// instruction. We do this only for addiw, slliw, and mulw because the -w forms
-// are less compressible.
+// instruction. We do this only for addw, slliw, and mulw because the -w forms
+// are less compressible: c.add and c.slli have a larger register encoding than
+// their w counterparts, and there's no compressible version of mulw.
 //
 //===---------------------------------------------------------------------===//