[llvm] f2f61a9 - [PowerPC] A fix for D159073. Do not optimize when register classes are different in src and dst.

[via llvm-commits]

Author: esmeyi
Date: 2023-09-26T09:28:26-04:00
New Revision: f2f61a99f7f754f3e4c819e1e7c65848affe70b3

URL: https://github.com/llvm/llvm-project/commit/f2f61a99f7f754f3e4c819e1e7c65848affe70b3
DIFF: https://github.com/llvm/llvm-project/commit/f2f61a99f7f754f3e4c819e1e7c65848affe70b3.diff

LOG: [PowerPC] A fix for D159073. Do not optimize when register classes are different in src and dst.

For example:
```
  %298:g8rc = RLDICL %297:g8rc, 0, 48
  %299:gprc = COPY killed %298.sub_32:g8rc
  dead %498:gprc = ANDI_rec killed %299:gprc, 1, implicit-def dead $cr0, implicit-def $cr0gt
```

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
index 5fd604b042f56c9..76a73436d61b545 100644
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -1214,6 +1214,14 @@ bool PPCMIPeephole::simplifyCode() {
         if (SrcOpCode != PPC::RLDICL && SrcOpCode != PPC::RLDICR)
           break;
 
+        Register SrcReg, DstReg;
+        SrcReg = SrcMI->getOperand(1).getReg();
+        DstReg = MI.getOperand(1).getReg();
+        const TargetRegisterClass *SrcRC = MRI->getRegClassOrNull(SrcReg);
+        const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(DstReg);
+        if (DstRC != SrcRC)
+          break;
+
         uint64_t AndImm = MI.getOperand(2).getImm();
         if (MI.getOpcode() == PPC::ANDIS_rec ||
             MI.getOpcode() == PPC::ANDIS8_rec)