[llvm] Late temporal divergence lowering for SDAG (PR #67033)

[via llvm-commits]

petar-avramovic wrote:

@nhaehnle  Let's start with https://github.com/llvm/llvm-project/blob/3f8ef57bede94445b1a1042c987cc914a886e7ff
It does not have good regression test (no temporal divergence), and issue it tries to fix was not an issue. However it stopped machine-sinking from sinking outside of the cycle (or after any si_end_cf). 
This way machine-sink can no longer introduce temporal divergent use - "bug fixed", but it can also no longer sink some instructions in cases where it was fine - "new performance bugs".

> Can you give a clean explanation of what this new pass does, referring to the definition of MIR semantics and nothing else?

We need a late pass that fixes sgpr defined inside cycle used outside the cycle with divergent exit.
Fix is to copy sgpr to vgpr inside the cycle and use that vgpr outside the cycle instead.

> The reason I'm asking is that this entire approach smells like accepting incorrect IR temporarily and then trying to fix it up later. That kind of approach always comes back to bite us in the end. We should not do it.

Temporal divergent use is just a simple use outside the cycle in IR, and I think that IR was fine.The temporal divergence errors are visible after register classes are assigned.
MIR is correct after SIFixSGPRCopies.cpp (temporal divergence is fixed by reassigned sgpr Src from inside the cycle to vgpr)

Now if there is a pass that can sink vgpr instruction outside of the cycle and instruction used sgpr Src defined inside the cycle we have a problem. Ideally we should place this pass late in the pipeline when other passes stop moving instructions outside the cycle.

Why this worked before is that everything was sunk outside of the cycles in IR passes and  there was nothing left for machine-sink to sink






https://github.com/llvm/llvm-project/pull/67033