[llvm] [RISCV][SelectionDAG] Sign extend splats of i32 in getConstant on RV64 (PR #67027)

[Luke Lau via llvm-commits]

lukel97 wrote:

Opened #67419. Would it still be useful to get this PR in? I think it would be good to improve the target independent case, even if `isSExtCheaperThanZExt` is only used by RISC-V

https://github.com/llvm/llvm-project/pull/67027