[llvm] [RISCV] Update comment on -w stripping pass. NFC (PR #67415)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

<details>
<summary>Changes</summary>

It looks like we only strip the -w suffix from addw and not addiw (bedcause c.addiw and c.addi have the same register encoding), but the comment in the header seems to have it the other way round.


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Full diff: https://github.com/llvm/llvm-project/pull/67415.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp (+4-3) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index bd294c669735f4f..3c608bf8b50b57d 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -12,10 +12,11 @@
 // extended bits aren't consumed or because the input was already sign extended
 // by an earlier instruction.
 //
-// Then it removes the -w suffix from each addiw and slliw instructions
+// Then it removes the -w suffix from addw, slliw and mulw instructions
 // whenever all users are dependent only on the lower word of the result of the
-// instruction. We do this only for addiw, slliw, and mulw because the -w forms
-// are less compressible.
+// instruction. We do this only for addw, slliw, and mulw because the -w forms
+// are less compressible: c.add and c.slli have a larger register encoding than
+// their w counterparts, and there's no compressible version of mulw.
 //
 //===---------------------------------------------------------------------===//
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/67415