[llvm] [RISCV] Disable constant hoisting for mul by one more/less than a pow… (PR #67385)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

<details>
<summary>Changes</summary>

…er of 2.

We can use a shift+add/sub for these. This often has same or lower latency than a multiply and may have more execution resources available.

---
Full diff: https://github.com/llvm/llvm-project/pull/67385.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp (+3) 
- (modified) llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll (+21-3) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 4a34362a792f150..1f069cb9eb514e4 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -127,6 +127,9 @@ InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
     // Power of 2 is a shift. Negated power of 2 is a shift and a negate.
     if (Imm.isPowerOf2() || Imm.isNegatedPowerOf2())
       return TTI::TCC_Free;
+    // One more or less than a power of 2 can use SLLI+ADD/SUB.
+    if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2())
+      return TTI::TCC_Free;
     // FIXME: There is no MULI instruction.
     Takes12BitImm = true;
     break;
diff --git a/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll b/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
index 4cf028d05780870..131ef673a61f829 100644
--- a/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
+++ b/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
@@ -22,9 +22,9 @@ define i64 @test2(i64 %a) nounwind {
 ; Check that we hoist immediates with large values.
 define i64 @test3(i64 %a) nounwind {
 ; CHECK-LABEL: test3
-; CHECK: %const = bitcast i64 32767 to i64
-  %1 = mul i64 %a, 32767
-  %2 = add i64 %1, 32767
+; CHECK: %const = bitcast i64 32766 to i64
+  %1 = mul i64 %a, 32766
+  %2 = add i64 %1, 32766
   ret i64 %2
 }
 
@@ -132,3 +132,21 @@ define i64 @test14(i64 %a) nounwind {
   ret i64 %2
 }
 
+; Check that we don't hoist mul by one less than a power of 2.
+define i64 @test15(i64 %a) nounwind {
+; CHECK-LABEL: test15
+; CHECK: mul i64 %a, 65535
+  %1 = mul i64 %a, 65535
+  %2 = mul i64 %1, 65535
+  ret i64 %2
+}
+
+; Check that we don't hoist mul by one more than a power of 2.
+define i64 @test16(i64 %a) nounwind {
+; CHECK-LABEL: test16
+; CHECK: mul i64 %a, 65537
+  %1 = mul i64 %a, 65537
+  %2 = mul i64 %1, 65537
+  ret i64 %2
+}
+

``````````

</details>


https://github.com/llvm/llvm-project/pull/67385