[llvm] [RISCV][GISel] Add instruction selection for G_SEXT, G_ZEXT, and G_SEXT_INREG (PR #67359)

Min-Yih Hsu via llvm-commits llvm-commits at lists.llvm.org
Mon Sep 25 15:08:26 PDT 2023

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https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/67359

Previous message: [llvm] [RISCV][GISel] Add instruction selection for G_SEXT, G_ZEXT, and G_SEXT_INREG (PR #67359)
Next message: [llvm] [ARM] Add writeback information to STC and LDC instructions. (PR #67180)
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