[llvm] [RISCV] Explicitly create IMPLICIT_DEF instead of UNDEF for vectors i… (PR #67369)

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llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

<details>
<summary>Changes</summary>

…n RISCVDAGToDAGISel::Select.

UNDEF needs to go through isel itself. All of the nodes have been topologically sorted so that instruction selection precedes from root to entry node. If we create a new node that needs to go through isel, we have to insert it into the correct place in the topological sort. If we don't, it might not get selected at all in some cases.

Some targets have a function like X86's insertDAGNode to sort newly created nodes.

To avoid introducing such a function on RISC-V, we can directly emit the IMPLICIT_DEF node that UNDEF would get selected to.

---
Full diff: https://github.com/llvm/llvm-project/pull/67369.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (+3-2) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 9a53c4a1297f500..5a5cd8c33ab369a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2104,8 +2104,9 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     if (IsStrided && !Subtarget->hasOptimizedZeroStrideLoad())
       break;
 
-    SmallVector<SDValue> Operands =
-      {CurDAG->getUNDEF(VT), Ld->getBasePtr()};
+    SmallVector<SDValue> Operands = {
+        SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, VT), 0),
+        Ld->getBasePtr()};
     if (IsStrided)
       Operands.push_back(CurDAG->getRegister(RISCV::X0, XLenVT));
     uint64_t Policy = RISCVII::MASK_AGNOSTIC | RISCVII::TAIL_AGNOSTIC;

``````````

</details>


https://github.com/llvm/llvm-project/pull/67369