[llvm] 7c9d7b7 - Revert "[AMDGPU] Add [[maybe_unused]] to several unused functions (NFC)"

[Kazu Hirata via llvm-commits]

Author: Kazu Hirata
Date: 2023-09-25T11:16:47-07:00
New Revision: 7c9d7b73e45508133ae606f10ac1416b4a4aca8b

URL: https://github.com/llvm/llvm-project/commit/7c9d7b73e45508133ae606f10ac1416b4a4aca8b
DIFF: https://github.com/llvm/llvm-project/commit/7c9d7b73e45508133ae606f10ac1416b4a4aca8b.diff

LOG: Revert "[AMDGPU] Add [[maybe_unused]] to several unused functions (NFC)"

This reverts commit fff16807c2e6c64d671b2f6b7b3ae76f5e16e38d.

We no longer need this workaround after
053478bbd0ae5329ea7993261225e6541f728858.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 33bbbf960c92b55..439762bc6caf786 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -262,9 +262,9 @@ DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW16, 16)
 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW32, 32)
 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(SReg_32, OPW32, 32)
 
-[[maybe_unused]] static DecodeStatus
-DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
-                           const MCDisassembler *Decoder) {
+static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm,
+                                               uint64_t /*Addr*/,
+                                               const MCDisassembler *Decoder) {
   assert(isUInt<10>(Imm) && "10-bit encoding expected");
   assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used");
 
@@ -274,7 +274,7 @@ DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
   return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
 }
 
-[[maybe_unused]] static DecodeStatus
+static DecodeStatus
 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
                                  const MCDisassembler *Decoder) {
   assert(isUInt<8>(Imm) && "8-bit encoding expected");
@@ -285,9 +285,9 @@ DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
   return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
 }
 
-[[maybe_unused]] static DecodeStatus
-decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
-                            const MCDisassembler *Decoder) {
+static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,
+                                                uint64_t /*Addr*/,
+                                                const MCDisassembler *Decoder) {
   assert(isUInt<9>(Imm) && "9-bit encoding expected");
 
   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
@@ -301,9 +301,9 @@ decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
                                                    Imm & 0xFF, false, 16));
 }
 
-[[maybe_unused]] static DecodeStatus
-decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
-                      const MCDisassembler *Decoder) {
+static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm,
+                                          uint64_t /*Addr*/,
+                                          const MCDisassembler *Decoder) {
   assert(isUInt<10>(Imm) && "10-bit encoding expected");
 
   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);