[llvm] fff1680 - [AMDGPU] Add [[maybe_unused]] to several unused functions (NFC)

[Kazu Hirata via llvm-commits]

Author: Kazu Hirata
Date: 2023-09-25T11:13:01-07:00
New Revision: fff16807c2e6c64d671b2f6b7b3ae76f5e16e38d

URL: https://github.com/llvm/llvm-project/commit/fff16807c2e6c64d671b2f6b7b3ae76f5e16e38d
DIFF: https://github.com/llvm/llvm-project/commit/fff16807c2e6c64d671b2f6b7b3ae76f5e16e38d.diff

LOG: [AMDGPU] Add [[maybe_unused]] to several unused functions (NFC)

Ivan is planning to introduce actual uses of these functions in near
future.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 439762bc6caf786..33bbbf960c92b55 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -262,9 +262,9 @@ DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW16, 16)
 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW32, 32)
 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(SReg_32, OPW32, 32)
 
-static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm,
-                                               uint64_t /*Addr*/,
-                                               const MCDisassembler *Decoder) {
+[[maybe_unused]] static DecodeStatus
+DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
+                           const MCDisassembler *Decoder) {
   assert(isUInt<10>(Imm) && "10-bit encoding expected");
   assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used");
 
@@ -274,7 +274,7 @@ static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm,
   return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
 }
 
-static DecodeStatus
+[[maybe_unused]] static DecodeStatus
 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
                                  const MCDisassembler *Decoder) {
   assert(isUInt<8>(Imm) && "8-bit encoding expected");
@@ -285,9 +285,9 @@ DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
   return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
 }
 
-static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,
-                                                uint64_t /*Addr*/,
-                                                const MCDisassembler *Decoder) {
+[[maybe_unused]] static DecodeStatus
+decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
+                            const MCDisassembler *Decoder) {
   assert(isUInt<9>(Imm) && "9-bit encoding expected");
 
   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
@@ -301,9 +301,9 @@ static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,
                                                    Imm & 0xFF, false, 16));
 }
 
-static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm,
-                                          uint64_t /*Addr*/,
-                                          const MCDisassembler *Decoder) {
+[[maybe_unused]] static DecodeStatus
+decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
+                      const MCDisassembler *Decoder) {
   assert(isUInt<10>(Imm) && "10-bit encoding expected");
 
   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);