[llvm] [RISCV] Match prefetch address with offset (PR #66072)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 25 11:13:02 PDT 2023
================
@@ -2351,7 +2357,8 @@ bool RISCVDAGToDAGISel::SelectAddrRegRegScale(SDValue Addr,
}
bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
- SDValue &Offset, bool IsINX) {
+ SDValue &Offset, bool IsINX,
+ bool IsPrefetch) {
if (SelectAddrFrameIndex(Addr, Base, Offset))
return true;
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topperc wrote:
Looks like the code below allows an ADD_LO to be matched, but you can't guarantee the final immediate has 0s in the least significant bits.
https://github.com/llvm/llvm-project/pull/66072
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