[llvm] 98e8f04 - Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFC.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 25 09:19:31 PDT 2023
Author: Simon Pilgrim
Date: 2023-09-25T17:19:21+01:00
New Revision: 98e8f04c9f9a1e063ac33053c6c86156016e5e48
URL: https://github.com/llvm/llvm-project/commit/98e8f04c9f9a1e063ac33053c6c86156016e5e48
DIFF: https://github.com/llvm/llvm-project/commit/98e8f04c9f9a1e063ac33053c6c86156016e5e48.diff
LOG: Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFC.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index c6a59ec44ef80e9..282a6ee149e50f0 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -2936,7 +2936,7 @@ bool AArch64InstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI,
if (avoidSlowSTRQ(MemI))
return false;
}
- return canFoldAddRegIntoAddrMode(1 << Shift);
+ return canFoldAddRegIntoAddrMode(1ULL << Shift);
}
case AArch64::ADDXrr:
@@ -2968,10 +2968,10 @@ bool AArch64InstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI,
if (Extend != AArch64_AM::UXTW && Extend != AArch64_AM::SXTW)
return false;
- return canFoldAddRegIntoAddrMode(1 << AArch64_AM::getArithShiftValue(Imm),
- (Extend == AArch64_AM::SXTW)
- ? ExtAddrMode::Formula::SExtScaledReg
- : ExtAddrMode::Formula::ZExtScaledReg);
+ return canFoldAddRegIntoAddrMode(
+ 1ULL << AArch64_AM::getArithShiftValue(Imm),
+ (Extend == AArch64_AM::SXTW) ? ExtAddrMode::Formula::SExtScaledReg
+ : ExtAddrMode::Formula::ZExtScaledReg);
}
}
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