[llvm] [NVPTX] Optimize v16i8 reductions (PR #67322)

[via llvm-commits]

github-actions[bot] wrote:


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git-clang-format --diff 97687b7aea17cfc6e9c42d89b6f22ac5b9c7ddc1 e3702e76e0c9fb4d7b335ccd71b16f2ca86d9e15 -- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index e425ffadf116..2ae16f0d992f 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -673,8 +673,8 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
 
   // We have some custom DAG combine patterns for these nodes
   setTargetDAGCombine({ISD::ADD, ISD::AND, ISD::FADD, ISD::MUL, ISD::SHL,
-                       ISD::SREM, ISD::UREM, ISD::EXTRACT_VECTOR_ELT,
-                       ISD::LOAD, ISD::ZERO_EXTEND});
+                       ISD::SREM, ISD::UREM, ISD::EXTRACT_VECTOR_ELT, ISD::LOAD,
+                       ISD::ZERO_EXTEND});
 
   // setcc for f16x2 and bf16x2 needs special handling to prevent
   // legalizer's attempt to scalarize it due to v2i1 not being legal.

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https://github.com/llvm/llvm-project/pull/67322