[llvm] [RISCV][CostModel] Add getCFInstrCost RISC-V implementation (PR #65599)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 25 02:25:44 PDT 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-analysis
<details>
<summary>Changes</summary>
This patch implements getCFInstrCost TTI hook that mostly affects
LoopVectorizer decisions. It sets zero cost for PHI nodes and zero
throughput cost for branches (assuming that branches are likely to
be predicted). The implementation is similar to X86/AArch64/PowerPC
targets and reduces loop cost by excluding induction PHIs/loop latch
branches, which in turn leads to selecting smaller vectorization
factor.
---
Patch is 435.20 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/65599.diff
55 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp (+9)
- (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h (+3)
- (modified) llvm/test/Analysis/CostModel/RISCV/abs.ll (+2-2)
- (modified) llvm/test/Analysis/CostModel/RISCV/active_lane_mask.ll (+1-1)
- (modified) llvm/test/Analysis/CostModel/RISCV/arith-fp.ll (+9-9)
- (modified) llvm/test/Analysis/CostModel/RISCV/arith-int.ll (+22-22)
- (modified) llvm/test/Analysis/CostModel/RISCV/cast.ll (+16-16)
- (modified) llvm/test/Analysis/CostModel/RISCV/fca-load-store.ll (+2-2)
- (modified) llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll (+1-1)
- (modified) llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll (+1-1)
- (modified) llvm/test/Analysis/CostModel/RISCV/fp-min-max-abs.ll (+6-6)
- (modified) llvm/test/Analysis/CostModel/RISCV/fp-sqrt-pow.ll (+2-2)
- (modified) llvm/test/Analysis/CostModel/RISCV/fp-trig-log-exp.ll (+7-7)
- (modified) llvm/test/Analysis/CostModel/RISCV/fround.ll (+14-14)
- (modified) llvm/test/Analysis/CostModel/RISCV/gep-zero-indices.ll (+10-10)
- (modified) llvm/test/Analysis/CostModel/RISCV/gep.ll (+8-8)
- (modified) llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll (+7-7)
- (modified) llvm/test/Analysis/CostModel/RISCV/int-min-max.ll (+4-4)
- (modified) llvm/test/Analysis/CostModel/RISCV/int-sat-math.ll (+6-6)
- (modified) llvm/test/Analysis/CostModel/RISCV/logicalop.ll (+2-2)
- (modified) llvm/test/Analysis/CostModel/RISCV/masked_ldst.ll (+2-2)
- (modified) llvm/test/Analysis/CostModel/RISCV/phi-const.ll (+50-50)
- (modified) llvm/test/Analysis/CostModel/RISCV/reduce-add.ll (+5-5)
- (modified) llvm/test/Analysis/CostModel/RISCV/reduce-and.ll (+5-5)
- (modified) llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll (+6-6)
- (modified) llvm/test/Analysis/CostModel/RISCV/reduce-max.ll (+10-10)
- (modified) llvm/test/Analysis/CostModel/RISCV/reduce-min.ll (+10-10)
- (modified) llvm/test/Analysis/CostModel/RISCV/reduce-or.ll (+5-5)
- (modified) llvm/test/Analysis/CostModel/RISCV/reduce-scalable-fp.ll (+67-67)
- (modified) llvm/test/Analysis/CostModel/RISCV/reduce-scalable-int.ll (+114-114)
- (modified) llvm/test/Analysis/CostModel/RISCV/reduce-xor.ll (+5-5)
- (modified) llvm/test/Analysis/CostModel/RISCV/rvv-cmp.ll (+22-22)
- (modified) llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll (+12-12)
- (modified) llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll (+12-12)
- (modified) llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll (+6-6)
- (modified) llvm/test/Analysis/CostModel/RISCV/rvv-load-store.ll (+3-3)
- (modified) llvm/test/Analysis/CostModel/RISCV/rvv-phi-const.ll (+130-130)
- (modified) llvm/test/Analysis/CostModel/RISCV/rvv-select.ll (+1-1)
- (modified) llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll (+4-4)
- (modified) llvm/test/Analysis/CostModel/RISCV/scalable-gather.ll (+4-4)
- (modified) llvm/test/Analysis/CostModel/RISCV/scalable-scatter.ll (+4-4)
- (modified) llvm/test/Analysis/CostModel/RISCV/shuffle-broadcast.ll (+2-2)
- (modified) llvm/test/Analysis/CostModel/RISCV/shuffle-extract_subvector.ll (+5-5)
- (modified) llvm/test/Analysis/CostModel/RISCV/shuffle-insert.ll (+8-8)
- (modified) llvm/test/Analysis/CostModel/RISCV/shuffle-insert_subvector.ll (+6-6)
- (modified) llvm/test/Analysis/CostModel/RISCV/shuffle-interleave.ll (+6-6)
- (modified) llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll (+2-2)
- (modified) llvm/test/Analysis/CostModel/RISCV/shuffle-reverse.ll (+1-1)
- (modified) llvm/test/Analysis/CostModel/RISCV/shuffle-select.ll (+4-4)
- (modified) llvm/test/Analysis/CostModel/RISCV/shuffle-transpose.ll (+24-24)
- (modified) llvm/test/Analysis/CostModel/RISCV/splice.ll (+1-1)
- (modified) llvm/test/Analysis/CostModel/RISCV/stepvector.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll (+3-3)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll (+16-14)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll (+19-12)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 6b950cd8a49fc09..4a34362a792f150 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1437,6 +1437,15 @@ InstructionCost RISCVTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
}
+InstructionCost RISCVTTIImpl::getCFInstrCost(unsigned Opcode,
+ TTI::TargetCostKind CostKind,
+ const Instruction *I) {
+ if (CostKind != TTI::TCK_RecipThroughput)
+ return Opcode == Instruction::PHI ? 0 : 1;
+ // Branches are assumed to be predicted.
+ return 0;
+}
+
InstructionCost RISCVTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
TTI::TargetCostKind CostKind,
unsigned Index, Value *Op0,
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index f836799649c26d7..81a45f623d294e8 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -169,6 +169,9 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
TTI::TargetCostKind CostKind,
const Instruction *I = nullptr);
+ InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
+ const Instruction *I = nullptr);
+
using BaseT::getVectorInstrCost;
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
TTI::TargetCostKind CostKind,
diff --git a/llvm/test/Analysis/CostModel/RISCV/abs.ll b/llvm/test/Analysis/CostModel/RISCV/abs.ll
index 1929a631fc41acd..c9d5c8d18df851d 100644
--- a/llvm/test/Analysis/CostModel/RISCV/abs.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/abs.ll
@@ -75,7 +75,7 @@ define i32 @abs(i32 %arg) {
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %30 = call <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %31 = call <vscale x 32 x i8> @llvm.abs.nxv32i8(<vscale x 32 x i8> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %32 = call <vscale x 64 x i8> @llvm.abs.nxv64i8(<vscale x 64 x i8> undef, i1 false)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
call <2 x i64> @llvm.abs.v2i64(<2 x i64> undef, i1 false)
call <4 x i64> @llvm.abs.v4i64(<4 x i64> undef, i1 false)
@@ -114,4 +114,4 @@ define i32 @abs(i32 %arg) {
call <vscale x 64 x i8> @llvm.abs.nxv64i8(<vscale x 64 x i8> undef, i1 false)
ret i32 undef
-}
\ No newline at end of file
+}
diff --git a/llvm/test/Analysis/CostModel/RISCV/active_lane_mask.ll b/llvm/test/Analysis/CostModel/RISCV/active_lane_mask.ll
index 71dac08a4b8ec32..ba62056f5851bd4 100644
--- a/llvm/test/Analysis/CostModel/RISCV/active_lane_mask.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/active_lane_mask.ll
@@ -25,7 +25,7 @@ define void @get_lane_mask() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_v2i1_i32 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %mask_v32i1_i64 = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 undef, i64 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %mask_v16i1_i16 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i16(i16 undef, i16 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
%mask_nxv16i1_i64 = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 undef, i64 undef)
%mask_nxv8i1_i64 = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i64(i64 undef, i64 undef)
diff --git a/llvm/test/Analysis/CostModel/RISCV/arith-fp.ll b/llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
index b0d071f808443b1..306277e46fa5b3d 100644
--- a/llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
@@ -38,7 +38,7 @@ define i32 @fadd() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2F64 = fadd <vscale x 2 x double> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4F64 = fadd <vscale x 4 x double> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8F64 = fadd <vscale x 8 x double> undef, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%F16 = fadd half undef, undef
%F32 = fadd float undef, undef
@@ -118,7 +118,7 @@ define i32 @fsub() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2F64 = fsub <vscale x 2 x double> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4F64 = fsub <vscale x 4 x double> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8F64 = fsub <vscale x 8 x double> undef, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%F16 = fsub half undef, undef
%F32 = fsub float undef, undef
@@ -198,7 +198,7 @@ define i32 @fmul() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2F64 = fmul <vscale x 2 x double> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4F64 = fmul <vscale x 4 x double> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8F64 = fmul <vscale x 8 x double> undef, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%F16 = fmul half undef, undef
%F32 = fmul float undef, undef
@@ -278,7 +278,7 @@ define i32 @fdiv() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2F64 = fdiv <vscale x 2 x double> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4F64 = fdiv <vscale x 4 x double> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8F64 = fdiv <vscale x 8 x double> undef, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%F16 = fdiv half undef, undef
%F32 = fdiv float undef, undef
@@ -358,7 +358,7 @@ define i32 @frem() {
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %NXV2F64 = frem <vscale x 2 x double> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %NXV4F64 = frem <vscale x 4 x double> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %NXV8F64 = frem <vscale x 8 x double> undef, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%F16 = frem half undef, undef
%F32 = frem float undef, undef
@@ -438,7 +438,7 @@ define i32 @fneg() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2F64 = fneg <vscale x 2 x double> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4F64 = fneg <vscale x 4 x double> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8F64 = fneg <vscale x 8 x double> undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%F16 = fneg half undef
%F32 = fneg float undef
@@ -518,7 +518,7 @@ define i32 @fcopysign() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2F64 = call <vscale x 2 x double> @llvm.copysign.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4F64 = call <vscale x 4 x double> @llvm.copysign.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8F64 = call <vscale x 8 x double> @llvm.copysign.nxv8f64(<vscale x 8 x double> undef, <vscale x 8 x double> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%F16 = call half @llvm.copysign.f16(half undef, half undef)
%F32 = call float @llvm.copysign.f32(float undef, float undef)
@@ -598,7 +598,7 @@ define i32 @fma() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2F64 = call <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4F64 = call <vscale x 4 x double> @llvm.fma.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, <vscale x 4 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8F64 = call <vscale x 8 x double> @llvm.fma.nxv8f64(<vscale x 8 x double> undef, <vscale x 8 x double> undef, <vscale x 8 x double> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%F16 = call half @llvm.fma.f16(half undef, half undef, half undef)
%F32 = call float @llvm.fma.f32(float undef, float undef, float undef)
@@ -675,7 +675,7 @@ define void @fmuladd() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %28 = call <vscale x 4 x double> @llvm.fmuladd.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, <vscale x 4 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %29 = call <vscale x 8 x double> @llvm.fmuladd.nxv8f64(<vscale x 8 x double> undef, <vscale x 8 x double> undef, <vscale x 8 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %30 = call <vscale x 16 x double> @llvm.fmuladd.nxv16f64(<vscale x 16 x double> undef, <vscale x 16 x double> undef, <vscale x 16 x double> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
call half @llvm.fmuladd.f16(half undef, half undef, half undef)
call float @llvm.fmuladd.f32(float undef, float undef, float undef)
diff --git a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
index 0f27fd9a4cee13a..00f2cd7b63a4a43 100644
--- a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
@@ -39,7 +39,7 @@ define i32 @add() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = add <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = add <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = add <vscale x 8 x i64> undef, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; SIFIVE-X280-LABEL: 'add'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = add i16 undef, undef
@@ -75,7 +75,7 @@ define i32 @add() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2I64 = add <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV4I64 = add <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV8I64 = add <vscale x 8 x i64> undef, undef
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%I16 = add i16 undef, undef
%I32 = add i32 undef, undef
@@ -155,7 +155,7 @@ define i32 @sub() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = sub <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = sub <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = sub <vscale x 8 x i64> undef, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; SIFIVE-X280-LABEL: 'sub'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = sub i16 undef, undef
@@ -191,7 +191,7 @@ define i32 @sub() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2I64 = sub <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV4I64 = sub <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV8I64 = sub <vscale x 8 x i64> undef, undef
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%I16 = sub i16 undef, undef
%I32 = sub i32 undef, undef
@@ -271,7 +271,7 @@ define i32 @mul() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = mul <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = mul <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = mul <vscale x 8 x i64> undef, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; SIFIVE-X280-LABEL: 'mul'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = mul i16 undef, undef
@@ -307,7 +307,7 @@ define i32 @mul() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2I64 = mul <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV4I64 = mul <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV8I64 = mul <vscale x 8 x i64> undef, undef
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%I16 = mul i16 undef, undef
%I32 = mul i32 undef, undef
@@ -387,7 +387,7 @@ define i32 @shl() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = shl <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = shl <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = shl <vscale x 8 x i64> undef, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; SIFIVE-X280-LABEL: 'shl'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = shl i16 undef, undef
@@ -423,7 +423,7 @@ define i32 @shl() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2I64 = shl <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV4I64 = shl <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV8I64 = shl <vscale x 8 x i64> undef, undef
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%I16 = shl i16 undef, undef
%I32 = shl i32 undef, undef
@@ -503,7 +503,7 @@ define i32 @lshr() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = lshr <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = lshr <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = lshr <vscale x 8 x i64> undef, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; SIFIVE-X280-LABEL: 'lshr'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = lshr i16 undef, undef
@@ -539,7 +539,7 @@ define i32 @lshr() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2I64 = lshr <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV4I64 = lshr <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV8I64 = lshr <vscale x 8 x i64> undef, undef
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%I16 = lshr i16 undef, undef
%I32 = lshr i32 undef, undef
@@ -619,7 +619,7 @@ define i32 @ashr() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = ashr <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = ashr <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = ashr <vscale x 8 x i64> undef, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; SIFIVE-X280-LABEL: 'ashr'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = ashr i16 undef, undef
@@ -655,7 +655,7 @@ define i32 @ashr() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2I64 = ashr <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV4I64 = ashr <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV8I64 = ashr <vscale x 8 x i64> undef, undef
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%I16 = ashr i16 undef, undef
%I32 = ashr i32 undef, undef
@@ -735,7 +735,7 @@ define i32 @udiv() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = udiv <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = udiv <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I64 = udiv <vscale x 8 x i64> un...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/65599
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