[llvm] 79af1cb - [GlobalISel] Add wrapper classes for G_INDEXED_LOAD/G_INDEXED_STORE

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2023-09-25T00:32:36-07:00
New Revision: 79af1cbbb2bb5077be053ab6ce841010b8e0bb00

URL: https://github.com/llvm/llvm-project/commit/79af1cbbb2bb5077be053ab6ce841010b8e0bb00
DIFF: https://github.com/llvm/llvm-project/commit/79af1cbbb2bb5077be053ab6ce841010b8e0bb00.diff

LOG: [GlobalISel] Add wrapper classes for G_INDEXED_LOAD/G_INDEXED_STORE

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
index ee515e469762efd..6c36b1bbcf8649b 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
@@ -36,13 +36,9 @@ class GenericMachineInstr : public MachineInstr {
   }
 };
 
-/// Represents any type of generic load or store.
-/// G_LOAD, G_STORE, G_ZEXTLOAD, G_SEXTLOAD.
-class GLoadStore : public GenericMachineInstr {
+/// Provides common memory operand functionality.
+class GMemOperation : public GenericMachineInstr {
 public:
-  /// Get the source register of the pointer value.
-  Register getPointerReg() const { return getOperand(1).getReg(); }
-
   /// Get the MachineMemOperand on this instruction.
   MachineMemOperand &getMMO() const { return **memoperands_begin(); }
 
@@ -62,6 +58,18 @@ class GLoadStore : public GenericMachineInstr {
   } /// Returns the size in bits of the memory access.
   uint64_t getMemSizeInBits() const { return getMMO().getSizeInBits(); }
 
+  static bool classof(const MachineInstr *MI) {
+    return GenericMachineInstr::classof(MI) && MI->hasOneMemOperand();
+  }
+};
+
+/// Represents any type of generic load or store.
+/// G_LOAD, G_STORE, G_ZEXTLOAD, G_SEXTLOAD.
+class GLoadStore : public GMemOperation {
+public:
+  /// Get the source register of the pointer value.
+  Register getPointerReg() const { return getOperand(1).getReg(); }
+
   static bool classof(const MachineInstr *MI) {
     switch (MI->getOpcode()) {
     case TargetOpcode::G_LOAD:
@@ -75,6 +83,73 @@ class GLoadStore : public GenericMachineInstr {
   }
 };
 
+/// Represents indexed loads. These are 
diff erent enough from regular loads
+/// that they get their own class. Including them in GAnyLoad would probably
+/// make a footgun for someone.
+class GIndexedLoad : public GMemOperation {
+public:
+  /// Get the definition register of the loaded value.
+  Register getDstReg() const { return getOperand(0).getReg(); }
+  /// Get the def register of the writeback value.
+  Register getWritebackReg() const { return getOperand(1).getReg(); }
+  /// Get the base register of the pointer value.
+  Register getBaseReg() const { return getOperand(2).getReg(); }
+  /// Get the offset register of the pointer value.
+  Register getOffsetReg() const { return getOperand(3).getReg(); }
+
+  bool isPre() const { return getOperand(5).getImm() == 1; }
+  bool isPost() const { return !isPre(); }
+
+  static bool classof(const MachineInstr *MI) {
+    return MI->getOpcode() == TargetOpcode::G_INDEXED_LOAD;
+  }
+};
+
+/// Represents a G_INDEX_ZEXTLOAD/G_INDEXED_SEXTLOAD.
+class GIndexedExtLoad : public GIndexedLoad {
+public:
+  static bool classof(const MachineInstr *MI) {
+    return MI->getOpcode() == TargetOpcode::G_INDEXED_SEXTLOAD ||
+           MI->getOpcode() == TargetOpcode::G_INDEXED_ZEXTLOAD;
+  }
+};
+
+/// Represents a G_ZEXTLOAD.
+class GIndexedZExtLoad : GIndexedExtLoad {
+public:
+  static bool classof(const MachineInstr *MI) {
+    return MI->getOpcode() == TargetOpcode::G_INDEXED_ZEXTLOAD;
+  }
+};
+
+/// Represents a G_SEXTLOAD.
+class GIndexedSExtLoad : GIndexedExtLoad {
+public:
+  static bool classof(const MachineInstr *MI) {
+    return MI->getOpcode() == TargetOpcode::G_INDEXED_SEXTLOAD;
+  }
+};
+
+/// Represents indexed stores.
+class GIndexedStore : public GMemOperation {
+public:
+  /// Get the def register of the writeback value.
+  Register getWritebackReg() const { return getOperand(0).getReg(); }
+  /// Get the stored value register.
+  Register getValueReg() const { return getOperand(1).getReg(); }
+  /// Get the base register of the pointer value.
+  Register getBaseReg() const { return getOperand(2).getReg(); }
+  /// Get the offset register of the pointer value.
+  Register getOffsetReg() const { return getOperand(3).getReg(); }
+
+  bool isPre() const { return getOperand(4).getImm() == 1; }
+  bool isPost() const { return !isPre(); }
+
+  static bool classof(const MachineInstr *MI) {
+    return MI->getOpcode() == TargetOpcode::G_INDEXED_STORE;
+  }
+};
+
 /// Represents any generic load, including sign/zero extending variants.
 class GAnyLoad : public GLoadStore {
 public: