[llvm] [SPIRV] Implement support for SPV_KHR_expect_assume (PR #66217)
Paulo Matos via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 25 00:16:21 PDT 2023
https://github.com/pmatos updated https://github.com/llvm/llvm-project/pull/66217
>From 54ec0051d672a3d117314989649452ba677fd142 Mon Sep 17 00:00:00 2001
From: Paulo Matos <pmatos at igalia.com>
Date: Wed, 13 Sep 2023 16:59:21 +0200
Subject: [PATCH 1/6] [SPIRV] Implement support for SPV_KHR_expect_assume
Adds new extension SPV_KHR_expect_assume, new capability
ExpectAssumeKHR as well as the new instructions:
* OpExpectKHR
* OpAssumeTrueKHR
These are lowered from respectively llvm.expect.<ty> and llvm.assume
intrinsics.
Differential Revision: https://reviews.llvm.org/D157696
---
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 6 +++-
llvm/lib/Target/SPIRV/SPIRVBuiltins.td | 1 +
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 4 +++
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 12 +++++++
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 5 +++
.../Target/SPIRV/SPIRVPrepareFunctions.cpp | 32 +++++++++++++++++++
.../lib/Target/SPIRV/SPIRVSymbolicOperands.td | 1 +
llvm/test/CodeGen/SPIRV/assume.ll | 15 +++++++++
llvm/test/CodeGen/SPIRV/expect.ll | 20 ++++++++++++
9 files changed, 95 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/SPIRV/assume.ll
create mode 100644 llvm/test/CodeGen/SPIRV/expect.ll
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index c06f77a05c051e3..efd195cf006615a 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -33,4 +33,8 @@ let TargetPrefix = "spv" in {
def int_spv_unreachable : Intrinsic<[], []>;
def int_spv_alloca : Intrinsic<[llvm_any_ty], []>;
def int_spv_undef : Intrinsic<[llvm_i32_ty], []>;
-}
+
+ // Expect, Assume Intrinsics
+ def int_spv_assume : Intrinsic<[], [llvm_i1_ty]>;
+ def int_spv_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>;
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
index 8acd4691787e4c6..ca6ac0581a3f709 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
@@ -54,6 +54,7 @@ def Enqueue : BuiltinGroup;
def AsyncCopy : BuiltinGroup;
def VectorLoadStore : BuiltinGroup;
def LoadStore : BuiltinGroup;
+def ExpectAssume : BuiltinGroup;
//===----------------------------------------------------------------------===//
// Class defining a demangled builtin record. The information in the record
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 5f3bc30591fa590..3736eb7c6604ef8 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -757,3 +757,7 @@ def OpGroupNonUniformBitwiseXor: OpGroupNUGroup<"BitwiseXor", 361>;
def OpGroupNonUniformLogicalAnd: OpGroupNUGroup<"LogicalAnd", 362>;
def OpGroupNonUniformLogicalOr: OpGroupNUGroup<"LogicalOr", 363>;
def OpGroupNonUniformLogicalXor: OpGroupNUGroup<"LogicalXor", 364>;
+
+// SPV_KHR_expect_assume : Expect assume instructions
+def OpAssumeTrueKHR: Op<5630, (outs), (ins ID:$cond), "OpAssumeTrueKHR $cond">;
+def OpExpectKHR: Op<5631, (outs ID:$res), (ins TYPE:$ty, ID:$val, ID:$expected), "$res = OpExpectKHR $ty $val $expected">;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index afa34ff3ce1fa40..febd4259e4e20f6 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -12,6 +12,7 @@
//
//===----------------------------------------------------------------------===//
+#include "MCTargetDesc/SPIRVMCTargetDesc.h"
#include "SPIRV.h"
#include "SPIRVGlobalRegistry.h"
#include "SPIRVInstrInfo.h"
@@ -1395,6 +1396,17 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
break;
case Intrinsic::spv_alloca:
return selectFrameIndex(ResVReg, ResType, I);
+ case Intrinsic::spv_assume:
+ BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpAssumeTrueKHR))
+ .addUse(I.getOperand(1).getReg());
+ break;
+ case Intrinsic::spv_expect:
+ BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExpectKHR))
+ .addDef(ResVReg)
+ .addUse(GR.getSPIRVTypeID(ResType))
+ .addUse(I.getOperand(2).getReg())
+ .addUse(I.getOperand(3).getReg());
+ break;
default:
llvm_unreachable("Intrinsic selection not implemented");
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index 66deb6fe42fcb83..35627cbe5d10e50 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -903,6 +903,11 @@ void addInstrRequirements(const MachineInstr &MI,
case SPIRV::OpGroupNonUniformBallotFindMSB:
Reqs.addCapability(SPIRV::Capability::GroupNonUniformBallot);
break;
+ case SPIRV::OpAssumeTrueKHR:
+ case SPIRV::OpExpectKHR:
+ Reqs.addExtension(SPIRV::Extension::SPV_KHR_expect_assume);
+ Reqs.addCapability(SPIRV::Capability::ExpectAssumeKHR);
+ break;
default:
break;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp b/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
index 554e66988f09043..87a9a0e4fab845c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
@@ -24,6 +24,8 @@
#include "llvm/CodeGen/IntrinsicLowering.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/IntrinsicInst.h"
+#include "llvm/IR/Intrinsics.h"
+#include "llvm/IR/IntrinsicsSPIRV.h"
#include "llvm/Transforms/Utils/Cloning.h"
#include "llvm/Transforms/Utils/LowerMemIntrinsics.h"
@@ -233,6 +235,32 @@ static void buildUMulWithOverflowFunc(Function *UMulFunc) {
IRB.CreateRet(Res);
}
+static void lowerExpectAssume(IntrinsicInst *II) {
+ // If we cannot use the SPV_KHR_expect_assume extension, then we need to
+ // ignore the intrinsic and move on. It should be removed later on by LLVM.
+ // Otherwise we should lower the intrinsic to the corresponding SPIR-V
+ // instruction.
+ // For @llvm.assume we have OpAssumeTrueKHR.
+ // For @llvm.expect we have OpExpectKHR.
+ //
+ // We need to lower this into a builtin and then the builtin into a SPIR-V
+ // instruction.
+ if (II->getIntrinsicID() == Intrinsic::assume) {
+ Function *F = Intrinsic::getDeclaration(
+ II->getModule(), Intrinsic::SPVIntrinsics::spv_assume);
+ II->setCalledFunction(F);
+ } else if (II->getIntrinsicID() == Intrinsic::expect) {
+ Function *F = Intrinsic::getDeclaration(
+ II->getModule(), Intrinsic::SPVIntrinsics::spv_expect,
+ {II->getOperand(0)->getType()});
+ II->setCalledFunction(F);
+ } else {
+ llvm_unreachable("Unknown intrinsic");
+ }
+
+ return;
+}
+
static void lowerUMulWithOverflow(IntrinsicInst *UMulIntrinsic) {
// Get a separate function - otherwise, we'd have to rework the CFG of the
// current one. Then simply replace the intrinsic uses with a call to the new
@@ -270,6 +298,10 @@ bool SPIRVPrepareFunctions::substituteIntrinsicCalls(Function *F) {
} else if (II->getIntrinsicID() == Intrinsic::umul_with_overflow) {
lowerUMulWithOverflow(II);
Changed = true;
+ } else if (II->getIntrinsicID() == Intrinsic::assume ||
+ II->getIntrinsicID() == Intrinsic::expect) {
+ lowerExpectAssume(II);
+ Changed = true;
}
}
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index ab06f5308700bc5..ac92ee4a0756a50 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -451,6 +451,7 @@ defm CooperativeMatrixNV : CapabilityOperand<5357, 0, 0, [], [Shader]>;
defm ArbitraryPrecisionIntegersINTEL : CapabilityOperand<5844, 0, 0, [SPV_INTEL_arbitrary_precision_integers], [Int8, Int16]>;
defm OptNoneINTEL : CapabilityOperand<6094, 0, 0, [SPV_INTEL_optnone], []>;
defm BitInstructions : CapabilityOperand<6025, 0, 0, [SPV_KHR_bit_instructions], []>;
+defm ExpectAssumeKHR : CapabilityOperand<5629, 0, 0, [SPV_KHR_expect_assume], []>;
//===----------------------------------------------------------------------===//
// Multiclass used to define SourceLanguage enum values and at the same time
diff --git a/llvm/test/CodeGen/SPIRV/assume.ll b/llvm/test/CodeGen/SPIRV/assume.ll
new file mode 100644
index 000000000000000..50d532d200a3820
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/assume.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=spirv32-unknown-unknown < %s | FileCheck %s
+; RUN: llc -mtriple=spirv64-unknown-unknown < %s | FileCheck %s
+
+; CHECK: OpCapability ExpectAssumeKHR
+; CHECK-NEXT: OpExtension "SPV_KHR_expect_assume"
+
+declare void @llvm.assume(i1)
+
+; CHECK-DAG: %9 = OpIEqual %5 %6 %7
+; CHECK-NEXT: OpAssumeTrueKHR %9
+define void @assumeeq(i32 %x, i32 %y) {
+ %cmp = icmp eq i32 %x, %y
+ call void @llvm.assume(i1 %cmp)
+ ret void
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/SPIRV/expect.ll b/llvm/test/CodeGen/SPIRV/expect.ll
new file mode 100644
index 000000000000000..da7acfb7504dfee
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/expect.ll
@@ -0,0 +1,20 @@
+; RUN: llc -mtriple=spirv32-unknown-unknown < %s | FileCheck %s
+; RUN: llc -mtriple=spirv64-unknown-unknown < %s | FileCheck %s
+
+; CHECK: OpCapability ExpectAssumeKHR
+; CHECK-NEXT: OpExtension "SPV_KHR_expect_assume"
+
+declare i32 @llvm.expect.i32(i32, i32)
+declare i32 @getOne()
+
+; CHECK-DAG: %2 = OpTypeInt 32 0
+; CHECK-DAG: %6 = OpFunctionParameter %2
+; CHECK-DAG: %9 = OpIMul %2 %6 %8
+; CHECK-DAG: %10 = OpExpectKHR %2 %9 %6
+
+define i32 @test(i32 %x) {
+ %one = call i32 @getOne()
+ %val = mul i32 %x, %one
+ %v = call i32 @llvm.expect.i32(i32 %val, i32 %x)
+ ret i32 %v
+}
>From 8f92dc87395f55a56a3e4a815348e8148df58433 Mon Sep 17 00:00:00 2001
From: Paulo Matos <pmatos at igalia.com>
Date: Mon, 18 Sep 2023 12:36:45 +0200
Subject: [PATCH 2/6] Address comments from @iliya-diyachkov.
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.td | 1 -
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 7 ++++---
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 6 ++++--
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
index ca6ac0581a3f709..8acd4691787e4c6 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
@@ -54,7 +54,6 @@ def Enqueue : BuiltinGroup;
def AsyncCopy : BuiltinGroup;
def VectorLoadStore : BuiltinGroup;
def LoadStore : BuiltinGroup;
-def ExpectAssume : BuiltinGroup;
//===----------------------------------------------------------------------===//
// Class defining a demangled builtin record. The information in the record
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 3736eb7c6604ef8..4971707d004da84 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -91,6 +91,10 @@ def OpNop: SimpleOp<"OpNop", 0>;
def OpUndef: Op<1, (outs ID:$res), (ins TYPE:$type), "$res = OpUndef $type">;
def OpSizeOf: Op<321, (outs ID:$res), (ins TYPE:$ty, ID:$ptr), "$res = OpSizeOf $ty $ptr">;
+// - SPV_KHR_expect_assume : Expect assume instructions
+def OpAssumeTrueKHR: Op<5630, (outs), (ins ID:$cond), "OpAssumeTrueKHR $cond">;
+def OpExpectKHR: Op<5631, (outs ID:$res), (ins TYPE:$ty, ID:$val, ID:$expected), "$res = OpExpectKHR $ty $val $expected">;
+
// 3.42.2 Debug Instructions
def OpSourceContinued: Op<2, (outs), (ins StringImm:$str, variable_ops),
@@ -758,6 +762,3 @@ def OpGroupNonUniformLogicalAnd: OpGroupNUGroup<"LogicalAnd", 362>;
def OpGroupNonUniformLogicalOr: OpGroupNUGroup<"LogicalOr", 363>;
def OpGroupNonUniformLogicalXor: OpGroupNUGroup<"LogicalXor", 364>;
-// SPV_KHR_expect_assume : Expect assume instructions
-def OpAssumeTrueKHR: Op<5630, (outs), (ins ID:$cond), "OpAssumeTrueKHR $cond">;
-def OpExpectKHR: Op<5631, (outs ID:$res), (ins TYPE:$ty, ID:$val, ID:$expected), "$res = OpExpectKHR $ty $val $expected">;
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index 35627cbe5d10e50..cdaf3ff1f132e30 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -905,8 +905,10 @@ void addInstrRequirements(const MachineInstr &MI,
break;
case SPIRV::OpAssumeTrueKHR:
case SPIRV::OpExpectKHR:
- Reqs.addExtension(SPIRV::Extension::SPV_KHR_expect_assume);
- Reqs.addCapability(SPIRV::Capability::ExpectAssumeKHR);
+ if(ST.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) {
+ Reqs.addExtension(SPIRV::Extension::SPV_KHR_expect_assume);
+ Reqs.addCapability(SPIRV::Capability::ExpectAssumeKHR);
+ }
break;
default:
break;
>From d8e28ffafd54ee7a7b8ae8c60bca18343076c139 Mon Sep 17 00:00:00 2001
From: Paulo Matos <pmatos at igalia.com>
Date: Fri, 22 Sep 2023 12:22:01 +0200
Subject: [PATCH 3/6] Address comments.
---
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 1 -
llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp | 1 -
llvm/test/CodeGen/SPIRV/assume.ll | 2 +-
llvm/test/CodeGen/SPIRV/expect.ll | 2 +-
4 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 4971707d004da84..da033ba32624cc2 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -761,4 +761,3 @@ def OpGroupNonUniformBitwiseXor: OpGroupNUGroup<"BitwiseXor", 361>;
def OpGroupNonUniformLogicalAnd: OpGroupNUGroup<"LogicalAnd", 362>;
def OpGroupNonUniformLogicalOr: OpGroupNUGroup<"LogicalOr", 363>;
def OpGroupNonUniformLogicalXor: OpGroupNUGroup<"LogicalXor", 364>;
-
diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
index e4ad805f071b9a7..0c185f663b63f87 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
@@ -11,7 +11,6 @@
//===----------------------------------------------------------------------===//
#include "SPIRVSubtarget.h"
-#include "MCTargetDesc/SPIRVBaseInfo.h"
#include "SPIRV.h"
#include "SPIRVGlobalRegistry.h"
#include "SPIRVLegalizerInfo.h"
diff --git a/llvm/test/CodeGen/SPIRV/assume.ll b/llvm/test/CodeGen/SPIRV/assume.ll
index 50d532d200a3820..276bb35a322fe0e 100644
--- a/llvm/test/CodeGen/SPIRV/assume.ll
+++ b/llvm/test/CodeGen/SPIRV/assume.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=spirv32-unknown-unknown < %s | FileCheck %s
; RUN: llc -mtriple=spirv64-unknown-unknown < %s | FileCheck %s
-; CHECK: OpCapability ExpectAssumeKHR
+; CHECK: OpCapability ExpectAssumeKHR
; CHECK-NEXT: OpExtension "SPV_KHR_expect_assume"
declare void @llvm.assume(i1)
diff --git a/llvm/test/CodeGen/SPIRV/expect.ll b/llvm/test/CodeGen/SPIRV/expect.ll
index da7acfb7504dfee..1c7a9a6a7809118 100644
--- a/llvm/test/CodeGen/SPIRV/expect.ll
+++ b/llvm/test/CodeGen/SPIRV/expect.ll
@@ -4,7 +4,7 @@
; CHECK: OpCapability ExpectAssumeKHR
; CHECK-NEXT: OpExtension "SPV_KHR_expect_assume"
-declare i32 @llvm.expect.i32(i32, i32)
+declare i32 @llvm.expect.i32(i32, i32)
declare i32 @getOne()
; CHECK-DAG: %2 = OpTypeInt 32 0
>From ea957ff10116f63524a61e20ef84bd941c96cffc Mon Sep 17 00:00:00 2001
From: Paulo Matos <pmatos at igalia.com>
Date: Fri, 22 Sep 2023 12:48:26 +0200
Subject: [PATCH 4/6] Rerun clang-format
---
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index cdaf3ff1f132e30..e8529496b07e4c4 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -905,7 +905,7 @@ void addInstrRequirements(const MachineInstr &MI,
break;
case SPIRV::OpAssumeTrueKHR:
case SPIRV::OpExpectKHR:
- if(ST.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) {
+ if (ST.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) {
Reqs.addExtension(SPIRV::Extension::SPV_KHR_expect_assume);
Reqs.addCapability(SPIRV::Capability::ExpectAssumeKHR);
}
>From ca15e2938b60a7cd13c0fc885d190321e7670ca5 Mon Sep 17 00:00:00 2001
From: Paulo Matos <pmatos at igalia.com>
Date: Fri, 22 Sep 2023 18:18:37 +0200
Subject: [PATCH 5/6] left align
---
llvm/test/CodeGen/SPIRV/assume.ll | 2 +-
llvm/test/CodeGen/SPIRV/expect.ll | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/SPIRV/assume.ll b/llvm/test/CodeGen/SPIRV/assume.ll
index 276bb35a322fe0e..e47dbd35f957fb8 100644
--- a/llvm/test/CodeGen/SPIRV/assume.ll
+++ b/llvm/test/CodeGen/SPIRV/assume.ll
@@ -6,7 +6,7 @@
declare void @llvm.assume(i1)
-; CHECK-DAG: %9 = OpIEqual %5 %6 %7
+; CHECK-DAG: %9 = OpIEqual %5 %6 %7
; CHECK-NEXT: OpAssumeTrueKHR %9
define void @assumeeq(i32 %x, i32 %y) {
%cmp = icmp eq i32 %x, %y
diff --git a/llvm/test/CodeGen/SPIRV/expect.ll b/llvm/test/CodeGen/SPIRV/expect.ll
index 1c7a9a6a7809118..530ba7e5a49b09a 100644
--- a/llvm/test/CodeGen/SPIRV/expect.ll
+++ b/llvm/test/CodeGen/SPIRV/expect.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=spirv32-unknown-unknown < %s | FileCheck %s
; RUN: llc -mtriple=spirv64-unknown-unknown < %s | FileCheck %s
-; CHECK: OpCapability ExpectAssumeKHR
+; CHECK: OpCapability ExpectAssumeKHR
; CHECK-NEXT: OpExtension "SPV_KHR_expect_assume"
declare i32 @llvm.expect.i32(i32, i32)
>From af5ff04e42133b7ef35fbe434d17f324d8db001d Mon Sep 17 00:00:00 2001
From: Paulo Matos <pmatos at igalia.com>
Date: Mon, 25 Sep 2023 09:15:50 +0200
Subject: [PATCH 6/6] Add line at end of file.
---
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 2 +-
llvm/test/CodeGen/SPIRV/assume.ll | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index efd195cf006615a..736be8ca3212bf2 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -37,4 +37,4 @@ let TargetPrefix = "spv" in {
// Expect, Assume Intrinsics
def int_spv_assume : Intrinsic<[], [llvm_i1_ty]>;
def int_spv_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>;
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/SPIRV/assume.ll b/llvm/test/CodeGen/SPIRV/assume.ll
index e47dbd35f957fb8..679db5d88d4fbe7 100644
--- a/llvm/test/CodeGen/SPIRV/assume.ll
+++ b/llvm/test/CodeGen/SPIRV/assume.ll
@@ -12,4 +12,4 @@ define void @assumeeq(i32 %x, i32 %y) {
%cmp = icmp eq i32 %x, %y
call void @llvm.assume(i1 %cmp)
ret void
-}
\ No newline at end of file
+}
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