[PATCH] D159073: [PowerPC][Peephole] Combine rldicl/rldicr and andi/andis after isel.

Mon Sep 25 00:05:52 PDT 2023

shchenz added inline comments.

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Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1120
+        // We can eliminate ANDI_rec or ANDIS_rec if all bits to AND are
+        // already zero in the input.
+        if ((SrcOpCode == PPC::RLDICL && (RZeroAndImm + ImmSrc > 63)) ||
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If we know that `all bits to AND are already zero`, why not we can just delete the `RLDICL/RLDICR`, and set the operand 2 of `ANDI/ANDIS` to 0 to indicate that ANDI/ANDIS products 0 result here? To me that would be more simple and later pass may have the opportunity to do more optimizations based on the 0?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159073/new/

https://reviews.llvm.org/D159073