[llvm] cedf2ea - [RISCV] Teach RISCVMergeBaseOffset to handle BlockAddress

[via llvm-commits]

Author: wangpc
Date: 2023-09-18T11:47:14+08:00
New Revision: cedf2ea7b50fd23a4f68f2276ebd9322e100e1f6

URL: https://github.com/llvm/llvm-project/commit/cedf2ea7b50fd23a4f68f2276ebd9322e100e1f6
DIFF: https://github.com/llvm/llvm-project/commit/cedf2ea7b50fd23a4f68f2276ebd9322e100e1f6.diff

LOG: [RISCV] Teach RISCVMergeBaseOffset to handle BlockAddress

We can get `BlockAddress` in user code via `Labels as Values` so
we should be able to merge the access to `BlockAddress`.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D159429

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
    llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
index 855322b981fb63a..097e12a2cd59f0d 100644
--- a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
@@ -94,7 +94,8 @@ bool RISCVMergeBaseOffsetOpt::detectFoldable(MachineInstr &Hi,
   if (HiOp1.getTargetFlags() != ExpectedFlags)
     return false;
 
-  if (!(HiOp1.isGlobal() || HiOp1.isCPI()) || HiOp1.getOffset() != 0)
+  if (!(HiOp1.isGlobal() || HiOp1.isCPI() || HiOp1.isBlockAddress()) ||
+      HiOp1.getOffset() != 0)
     return false;
 
   Register HiDestReg = Hi.getOperand(0).getReg();
@@ -108,7 +109,8 @@ bool RISCVMergeBaseOffsetOpt::detectFoldable(MachineInstr &Hi,
   const MachineOperand &LoOp2 = Lo->getOperand(2);
   if (Hi.getOpcode() == RISCV::LUI) {
     if (LoOp2.getTargetFlags() != RISCVII::MO_LO ||
-        !(LoOp2.isGlobal() || LoOp2.isCPI()) || LoOp2.getOffset() != 0)
+        !(LoOp2.isGlobal() || LoOp2.isCPI() || LoOp2.isBlockAddress()) ||
+        LoOp2.getOffset() != 0)
       return false;
   } else {
     assert(Hi.getOpcode() == RISCV::AUIPC);
@@ -120,8 +122,10 @@ bool RISCVMergeBaseOffsetOpt::detectFoldable(MachineInstr &Hi,
   if (HiOp1.isGlobal()) {
     LLVM_DEBUG(dbgs() << "  Found lowered global address: "
                       << *HiOp1.getGlobal() << "\n");
-  } else {
-    assert(HiOp1.isCPI());
+  } else if (HiOp1.isBlockAddress()) {
+    LLVM_DEBUG(dbgs() << "  Found lowered basic address: "
+                      << *HiOp1.getBlockAddress() << "\n");
+  } else if (HiOp1.isCPI()) {
     LLVM_DEBUG(dbgs() << "  Found lowered constant pool: " << HiOp1.getIndex()
                       << "\n");
   }

diff  --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
index dd64a0f54261557..279f4628147f274 100644
--- a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
+++ b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
@@ -471,8 +471,7 @@ define dso_local ptr @load_ba_1() nounwind {
 ; RV32I-MEDIUM-NEXT:  # %bb.1: # %label
 ; RV32I-MEDIUM-NEXT:  .Lpcrel_hi12:
 ; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(.Ltmp0)
-; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi12)
-; RV32I-MEDIUM-NEXT:    lw a0, 0(a0)
+; RV32I-MEDIUM-NEXT:    lw a0, %pcrel_lo(.Lpcrel_hi12)(a0)
 ; RV32I-MEDIUM-NEXT:    ret
 ;
 ; RV64I-LABEL: load_ba_1:
@@ -489,8 +488,7 @@ define dso_local ptr @load_ba_1() nounwind {
 ; RV64I-MEDIUM-NEXT:  # %bb.1: # %label
 ; RV64I-MEDIUM-NEXT:  .Lpcrel_hi12:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(.Ltmp0)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi12)
-; RV64I-MEDIUM-NEXT:    ld a0, 0(a0)
+; RV64I-MEDIUM-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi12)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
 entry:
   br label %label
@@ -504,9 +502,8 @@ define dso_local ptr @load_ba_2() nounwind {
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:  .Ltmp1: # Block address taken
 ; RV32I-NEXT:  # %bb.1: # %label
-; RV32I-NEXT:    lui a0, %hi(.Ltmp1)
-; RV32I-NEXT:    addi a0, a0, %lo(.Ltmp1)
-; RV32I-NEXT:    lw a0, 8(a0)
+; RV32I-NEXT:    lui a0, %hi(.Ltmp1+8)
+; RV32I-NEXT:    lw a0, %lo(.Ltmp1+8)(a0)
 ; RV32I-NEXT:    ret
 ;
 ; RV32I-MEDIUM-LABEL: load_ba_2:
@@ -514,18 +511,16 @@ define dso_local ptr @load_ba_2() nounwind {
 ; RV32I-MEDIUM-NEXT:  .Ltmp1: # Block address taken
 ; RV32I-MEDIUM-NEXT:  # %bb.1: # %label
 ; RV32I-MEDIUM-NEXT:  .Lpcrel_hi13:
-; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(.Ltmp1)
-; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi13)
-; RV32I-MEDIUM-NEXT:    lw a0, 8(a0)
+; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(.Ltmp1+8)
+; RV32I-MEDIUM-NEXT:    lw a0, %pcrel_lo(.Lpcrel_hi13)(a0)
 ; RV32I-MEDIUM-NEXT:    ret
 ;
 ; RV64I-LABEL: load_ba_2:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:  .Ltmp1: # Block address taken
 ; RV64I-NEXT:  # %bb.1: # %label
-; RV64I-NEXT:    lui a0, %hi(.Ltmp1)
-; RV64I-NEXT:    addi a0, a0, %lo(.Ltmp1)
-; RV64I-NEXT:    ld a0, 8(a0)
+; RV64I-NEXT:    lui a0, %hi(.Ltmp1+8)
+; RV64I-NEXT:    ld a0, %lo(.Ltmp1+8)(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64I-MEDIUM-LABEL: load_ba_2:
@@ -533,9 +528,8 @@ define dso_local ptr @load_ba_2() nounwind {
 ; RV64I-MEDIUM-NEXT:  .Ltmp1: # Block address taken
 ; RV64I-MEDIUM-NEXT:  # %bb.1: # %label
 ; RV64I-MEDIUM-NEXT:  .Lpcrel_hi13:
-; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(.Ltmp1)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi13)
-; RV64I-MEDIUM-NEXT:    ld a0, 8(a0)
+; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(.Ltmp1+8)
+; RV64I-MEDIUM-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi13)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
 entry:
   br label %label