[llvm] [RISCV] Make InitUndef handle undef operand (PR #65755)
Piyou Chen via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 17 19:41:44 PDT 2023
================
@@ -134,53 +134,32 @@ static bool isEarlyClobberMI(MachineInstr &MI) {
});
}
-bool RISCVInitUndef::handleImplicitDef(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &Inst) {
- assert(Inst->getOpcode() == TargetOpcode::IMPLICIT_DEF);
-
- Register Reg = Inst->getOperand(0).getReg();
- if (!Reg.isVirtual())
- return false;
-
- bool HasOtherUse = false;
- SmallVector<MachineOperand *, 1> UseMOs;
- for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
- if (isEarlyClobberMI(*MO.getParent())) {
- if (MO.isUse() && !MO.isTied())
- UseMOs.push_back(&MO);
- else
- HasOtherUse = true;
- }
- }
-
- if (UseMOs.empty())
- return false;
-
- LLVM_DEBUG(
- dbgs() << "Emitting PseudoRVVInitUndef for implicit vector register "
- << Reg << '\n');
-
- const TargetRegisterClass *TargetRegClass =
- getVRLargestSuperClass(MRI->getRegClass(Reg));
- unsigned Opcode = getUndefInitOpcode(TargetRegClass->getID());
-
- Register NewDest = Reg;
- if (HasOtherUse) {
- NewDest = MRI->createVirtualRegister(TargetRegClass);
- // We don't have a way to update dead lanes, so keep track of the
- // new register so that we avoid querying it later.
- NewRegs.insert(NewDest);
+static bool findImplictDefMIFromReg(Register Reg, MachineRegisterInfo *MRI) {
+ for (auto &DefMI : MRI->def_instructions(Reg)) {
+ if (DefMI.getOpcode() == TargetOpcode::IMPLICIT_DEF)
+ return true;
}
- BuildMI(MBB, Inst, Inst->getDebugLoc(), TII->get(Opcode), NewDest);
+ return false;
+}
- if (!HasOtherUse)
- Inst = MBB.erase(Inst);
+bool RISCVInitUndef::handleReg(MachineInstr *MI) {
+ bool Changed = false;
+ for (auto &UseMO : MI->uses()) {
+ if (!UseMO.isReg())
+ continue;
+ if (UseMO.isTied())
+ continue;
+ if (!UseMO.getReg().isVirtual())
+ continue;
+ if (!isVectorRegClass(UseMO.getReg()))
+ continue;
+ if (UseMO.getReg() == 0)
----------------
BeMg wrote:
You're right. `$noreg` is not belong to virtual register.
Remove the `reg == 0` .
https://github.com/llvm/llvm-project/pull/65755
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