[llvm] [RISCV] Prefer vrgatherei16 for shuffles (PR #66291)
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 15 14:44:03 PDT 2023
================
@@ -4651,6 +4651,15 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
IndexVT = IndexVT.changeVectorElementType(MVT::i16);
}
+ // If the mask allows, we can do all the index computation in 16 bits. This
+ // requires less work and less register pressure at high LMUL, and creates
+ // smaller constants which may be cheaper to materialize.
+ if (IndexVT.getScalarType().bitsGT(MVT::i16) && isUInt<16>(NumElts * 2) &&
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preames wrote:
You're correct, and I will adjust. In practice, I'm not too worried about vectors with 32k elements. :)
https://github.com/llvm/llvm-project/pull/66291
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