[PATCH] D76445: [RISCV][GlobalISel] Select ALU GPR instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll:36
+; RV64IM:       # %bb.0: # %entry
+; RV64IM-NEXT:    slli a0, a0, 24
+; RV64IM-NEXT:    sraiw a0, a0, 24
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nitinjohnraj wrote:
> I think this should be slliw?
The upper bits aren’t used by the sraiw so SLLI should be ok


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Comment at: llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll:412
+; RV32IM-NEXT:    sltiu a2, a0, 1234
+; RV32IM-NEXT:    mv a1, a1
+; RV32IM-NEXT:    andi a2, a2, 1
----------------
nitinjohnraj wrote:
> Why is this instruction emitted? This looks like a nop.
> 
> We may want to handle this in a later pass.
The upper half immediate  is 0 and we don’t have combines enabled.


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Comment at: llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir:3
+# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: | FileCheck -check-prefix=RV32I %s
+
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nitinjohnraj wrote:
> Do we want tests for `and_i64`, `or_i64` and `xor_i64`? And immediate variants for these and `add_i64`, `sub_i64`?
I don’t think they provide any value. They would all be split instructions.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D76445/new/

https://reviews.llvm.org/D76445