[llvm] [CodeGen] Renumber slot indexes before register allocation (PR #66334)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 15 07:02:43 PDT 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
<details>
<summary>Changes</summary>
RegAllocGreedy uses SlotIndexes::getApproxInstrDistance to approximate
the length of a live range for its heuristics. Renumbering all slot
indexes with the default instruction distance ensures that this estimate
will be as accurate as possible, and will not depend on the history of
how instructions have been added to and removed from SlotIndexes's maps.
This also means that enabling -early-live-intervals, which runs the
SlotIndexes analysis earlier, will not cause large amounts of churn due
to different register allocator decisions.
--
Patch is 31.92 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/66334.diff
330 Files Affected:
- (modified) llvm/include/llvm/CodeGen/SlotIndexes.h (+3)
- (modified) llvm/lib/CodeGen/RegAllocGreedy.cpp (+3)
- (modified) llvm/lib/CodeGen/SlotIndexes.cpp (+5)
- (modified) llvm/test/CodeGen/AArch64/active_lane_mask.ll (+45-45)
- (modified) llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll (+12-12)
- (modified) llvm/test/CodeGen/AArch64/arm64-cse.ll (+5-5)
- (modified) llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll (+22-22)
- (modified) llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll (+16-16)
- (modified) llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll (+12-12)
- (modified) llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll (+11-11)
- (modified) llvm/test/CodeGen/AArch64/extbinopload.ll (+73-73)
- (modified) llvm/test/CodeGen/AArch64/faddp-half.ll (+5-5)
- (modified) llvm/test/CodeGen/AArch64/fcvt_combine.ll (+42-42)
- (modified) llvm/test/CodeGen/AArch64/fdiv.ll (+6-6)
- (modified) llvm/test/CodeGen/AArch64/fpow.ll (+93-93)
- (modified) llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll (+252-252)
- (modified) llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll (+88-90)
- (modified) llvm/test/CodeGen/AArch64/frem.ll (+93-93)
- (modified) llvm/test/CodeGen/AArch64/llvm.exp10.ll (+5-6)
- (modified) llvm/test/CodeGen/AArch64/neon-dotreduce.ll (+515-515)
- (modified) llvm/test/CodeGen/AArch64/neon-extadd.ll (+26-26)
- (modified) llvm/test/CodeGen/AArch64/pow.ll (+4-4)
- (modified) llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll (+109-116)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll (+18-18)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll (+26-26)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll (+50-50)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll (+40-40)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll (+74-72)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll (+95-95)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll (+11-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll (+204-204)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll (+1439-1434)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll (+119-119)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll (+1066-1062)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll (+312-312)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll (+297-296)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll (+268-268)
- (modified) llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll (+18-18)
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- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp2.ll (+13-13)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log2.ll (+13-13)
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- (modified) llvm/test/CodeGen/AMDGPU/swdev380865.ll (+2-4)
- (modified) llvm/test/CodeGen/AMDGPU/udiv.ll (+48-48)
- (modified) llvm/test/CodeGen/AMDGPU/urem64.ll (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/wave32.ll (+29-29)
- (modified) llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll (+6-6)
- (modified) llvm/test/CodeGen/Hexagon/autohvx/fp-to-int.ll (+62-60)
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- (modified) llvm/test/CodeGen/Hexagon/autohvx/isel-truncate.ll (+4-4)
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- (modified) llvm/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll (-1)
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- (modified) llvm/test/CodeGen/Hexagon/signext-inreg.ll (+23-23)
- (modified) llvm/test/CodeGen/Hexagon/swp-conv3x3-nested.ll (+2-1)
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- (modified) llvm/test/CodeGen/PowerPC/all-atomics.ll (+29-29)
- (modified) llvm/test/CodeGen/PowerPC/atomics.ll (+21-21)
- (modified) llvm/test/CodeGen/PowerPC/inc-of-add.ll (+71-69)
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- (modified) llvm/test/CodeGen/RISCV/callee-saved-gprs.ll (+96-96)
- (modified) llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll (+7-7)
- (modified) llvm/test/CodeGen/RISCV/fpclamptosat.ll (+32-32)
- (modified) llvm/test/CodeGen/RISCV/mul.ll (+28-28)
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- (modified) llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll (+2-2)
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<truncated>
</pre>
</details>
https://github.com/llvm/llvm-project/pull/66334
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