[PATCH] D158579: [AMDGPU] Add DAG ISel support for preloaded kernel arguments

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Also should do the globalisel equivalent



================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h:158
+  // Map the index of preloaded kernel arguments to its descriptor.
+  SmallDenseMap<int, KernArgPreloadDescriptor> PreloadKernArgs{};
+
----------------
Why is it a map? Isn't this just an array?


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp:223
+
+  if (MF->getInfo<SIMachineFunctionInfo>()->getNumKernargPreloadedSGPRs() > 0) {
+    assert(AMDGPU::hasKernargPreload(STM));
----------------



================
Comment at: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp:836-842
+bool AMDGPUTargetAsmStreamer::EmitKernargPreloadHeader(
+    const MCSubtargetInfo &STI) {
+  for (int i = 0; i < 64; ++i) {
+    OS << "\ts_nop 0\n";
+  }
+  return true;
+}
----------------
Shouldn't need this, there are already nop emission utilities?


================
Comment at: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp:848
+  MCStreamer &OS = getStreamer();
+  for (int i = 0; i < 64; ++i) {
+    OS.emitInt32(Encoded_s_nop);
----------------
emitValueToAlignment?


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:2239
+
+// Allocate pre-loaded kernel arguemtns. Arguments to be preloading must be
+// sequential starting from the first argument.
----------------



================
Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp:246
 
+SmallVectorImpl<MCRegister> *SIMachineFunctionInfo::addPreloadedKernArg(
+    const SIRegisterInfo &TRI, const TargetRegisterClass *RC,
----------------
This can return ArrayRef?


================
Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp:267
+  // Track the actual number of SGPRs that HW will preload to.
+  UserSGPRInfo.allocKerargPreloadSGPRs(AllocSizeDWord + PaddingSGPRs);
+  return &ArgInfo.PreloadKernArgs[KernArgIdx].Regs;
----------------
Typo Kerarg


================
Comment at: llvm/test/CodeGen/AMDGPU/preload-kernargs.ll:21
+; PRELOAD-1-LABEL: ptr1_i8:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
----------------
should be able to use a directive to avoid spamming this 


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  https://reviews.llvm.org/D158579/new/

https://reviews.llvm.org/D158579