[llvm] b0f0aa8 - [AArch64] Guard against a invalid size request in performVecReduceAddCombine

[David Green via llvm-commits]

Author: David Green
Date: 2023-09-15T14:04:21+01:00
New Revision: b0f0aa852d074441fc4dafc138a9cffc3d083dbc

URL: https://github.com/llvm/llvm-project/commit/b0f0aa852d074441fc4dafc138a9cffc3d083dbc
DIFF: https://github.com/llvm/llvm-project/commit/b0f0aa852d074441fc4dafc138a9cffc3d083dbc.diff

LOG: [AArch64] Guard against a invalid size request in performVecReduceAddCombine

With both +sve and +dotprod, and a scalable vecreduce(sext) we could attempt to
access the number of elements of a scalable vector. Guard against this for now,
until scalable dotprod are properly supported.

Added: 
    llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 30a66c7ae4be845..fd6068c9787e6c5 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -15969,7 +15969,7 @@ static SDValue performVecReduceAddCombine(SDNode *N, SelectionDAG &DAG,
     return performVecReduceAddCombineWithUADDLP(N, DAG);
 
   SDValue Op0 = N->getOperand(0);
-  if (N->getValueType(0) != MVT::i32 ||
+  if (N->getValueType(0) != MVT::i32 || Op0.getValueType().isScalableVT() ||
       Op0.getValueType().getVectorElementType() != MVT::i32)
     return SDValue();
 

diff  --git a/llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll b/llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
new file mode 100644
index 000000000000000..4d0d2a991d0e565
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
@@ -0,0 +1,54 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mattr=+sve,+dotprod < %s | FileCheck %s
+
+define i32 @test(<vscale x 32 x i8> %bin.rdx, <vscale x 32 x i8> %bin.rdx2)  {
+; CHECK-LABEL: test:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sunpklo z4.h, z2.b
+; CHECK-NEXT:    sunpklo z5.h, z0.b
+; CHECK-NEXT:    sunpkhi z0.h, z0.b
+; CHECK-NEXT:    sunpkhi z2.h, z2.b
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    sunpklo z6.h, z1.b
+; CHECK-NEXT:    sunpkhi z1.h, z1.b
+; CHECK-NEXT:    sunpklo z7.h, z3.b
+; CHECK-NEXT:    sunpkhi z3.h, z3.b
+; CHECK-NEXT:    sunpkhi z24.s, z5.h
+; CHECK-NEXT:    sunpklo z5.s, z5.h
+; CHECK-NEXT:    sunpklo z25.s, z4.h
+; CHECK-NEXT:    sunpklo z26.s, z0.h
+; CHECK-NEXT:    sunpkhi z4.s, z4.h
+; CHECK-NEXT:    sunpklo z27.s, z2.h
+; CHECK-NEXT:    sunpkhi z0.s, z0.h
+; CHECK-NEXT:    sunpkhi z2.s, z2.h
+; CHECK-NEXT:    sunpklo z28.s, z6.h
+; CHECK-NEXT:    sunpkhi z6.s, z6.h
+; CHECK-NEXT:    mul z5.s, p0/m, z5.s, z25.s
+; CHECK-NEXT:    sunpkhi z25.s, z1.h
+; CHECK-NEXT:    sunpklo z1.s, z1.h
+; CHECK-NEXT:    mul z26.s, p0/m, z26.s, z27.s
+; CHECK-NEXT:    mul z4.s, p0/m, z4.s, z24.s
+; CHECK-NEXT:    sunpkhi z24.s, z3.h
+; CHECK-NEXT:    mul z0.s, p0/m, z0.s, z2.s
+; CHECK-NEXT:    sunpkhi z2.s, z7.h
+; CHECK-NEXT:    sunpklo z3.s, z3.h
+; CHECK-NEXT:    sunpklo z7.s, z7.h
+; CHECK-NEXT:    mla z0.s, p0/m, z25.s, z24.s
+; CHECK-NEXT:    mad z2.s, p0/m, z6.s, z4.s
+; CHECK-NEXT:    mad z1.s, p0/m, z3.s, z26.s
+; CHECK-NEXT:    movprfx z3, z5
+; CHECK-NEXT:    mla z3.s, p0/m, z28.s, z7.s
+; CHECK-NEXT:    add z0.s, z2.s, z0.s
+; CHECK-NEXT:    add z1.s, z3.s, z1.s
+; CHECK-NEXT:    add z0.s, z1.s, z0.s
+; CHECK-NEXT:    uaddv d0, p0, z0.s
+; CHECK-NEXT:    fmov x0, d0
+; CHECK-NEXT:    // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT:    ret
+  %a = sext <vscale x 32 x i8> %bin.rdx to <vscale x 32 x i32>
+  %b = sext <vscale x 32 x i8> %bin.rdx2 to <vscale x 32 x i32>
+  %c = mul <vscale x 32 x i32> %a, %b
+  %r = call i32 @llvm.vector.reduce.add.nxv32i32(<vscale x 32 x i32> %c)
+  ret i32 %r
+}
+declare i32 @llvm.vector.reduce.add.nxv32i32(<vscale x 32 x i32> )