[llvm] 0a692b6 - [LoongArch] Fix incorrect instruction 'and' in pattern
Weining Lu via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 15 01:16:41 PDT 2023
Author: Weining Lu
Date: 2023-09-15T16:16:06+08:00
New Revision: 0a692b6b9632e1460f9e0e983196f2be5879acd1
URL: https://github.com/llvm/llvm-project/commit/0a692b6b9632e1460f9e0e983196f2be5879acd1
DIFF: https://github.com/llvm/llvm-project/commit/0a692b6b9632e1460f9e0e983196f2be5879acd1.diff
LOG: [LoongArch] Fix incorrect instruction 'and' in pattern
It should be `andi`, but not `and`.
Address buildbot failure:
https://lab.llvm.org/buildbot/#/builders/42/builds/11634
Added:
Modified:
llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
llvm/test/CodeGen/LoongArch/is_fpclass_f32.ll
llvm/test/CodeGen/LoongArch/is_fpclass_f64.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
index e01c721e9ee63b8..d4d8736ec0caaea 100644
--- a/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
@@ -156,8 +156,8 @@ def : PatFpr<fsqrt, FSQRT_S, FPR32>;
def : Pat<(fdiv fpimm1, (fsqrt FPR32:$fj)), (FRSQRT_S FPR32:$fj)>;
def : Pat<(fcanonicalize FPR32:$fj), (FMAX_S $fj, $fj)>;
def : Pat<(is_fpclass FPR32:$fj, (i32 timm:$mask)),
- (SLTU R0, (AND (MOVFR2GR_S (FCLASS_S FPR32:$fj)),
- (to_fclass_mask timm:$mask)))>;
+ (SLTU R0, (ANDI (MOVFR2GR_S (FCLASS_S FPR32:$fj)),
+ (to_fclass_mask timm:$mask)))>;
/// Setcc
diff --git a/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
index 693e06cd4fd8b57..c2103b02b448a42 100644
--- a/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
@@ -150,13 +150,13 @@ def : Pat<(fcopysign FPR32:$fj, FPR64:$fk),
def : Pat<(fcanonicalize FPR64:$fj), (FMAX_D $fj, $fj)>;
let Predicates = [IsLA32] in {
def : Pat<(is_fpclass FPR64:$fj, (i32 timm:$mask)),
- (SLTU R0, (AND (MOVFR2GR_S_64 (FCLASS_D FPR64:$fj)),
- (to_fclass_mask timm:$mask)))>;
+ (SLTU R0, (ANDI (MOVFR2GR_S_64 (FCLASS_D FPR64:$fj)),
+ (to_fclass_mask timm:$mask)))>;
} // Predicates = [IsLA32]
let Predicates = [IsLA64] in {
def : Pat<(is_fpclass FPR64:$fj, (i32 timm:$mask)),
- (SLTU R0, (AND (MOVFR2GR_D (FCLASS_D FPR64:$fj)),
- (to_fclass_mask timm:$mask)))>;
+ (SLTU R0, (ANDI (MOVFR2GR_D (FCLASS_D FPR64:$fj)),
+ (to_fclass_mask timm:$mask)))>;
} // Predicates = [IsLA64]
/// Setcc
diff --git a/llvm/test/CodeGen/LoongArch/is_fpclass_f32.ll b/llvm/test/CodeGen/LoongArch/is_fpclass_f32.ll
index 095d6560e867127..af128fa52e1d2e2 100644
--- a/llvm/test/CodeGen/LoongArch/is_fpclass_f32.ll
+++ b/llvm/test/CodeGen/LoongArch/is_fpclass_f32.ll
@@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc --mtriple=loongarch32 --mattr=+f < %s | FileCheck %s
-; RUN: llc --mtriple=loongarch64 --mattr=+f < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+f --verify-machineinstrs < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+f --verify-machineinstrs < %s | FileCheck %s
define i1 @isnan_f(float %x) {
; CHECK-LABEL: isnan_f:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 3
+; CHECK-NEXT: andi $a0, $a0, 3
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -20,7 +20,7 @@ define i1 @isnot_nan_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 1020
+; CHECK-NEXT: andi $a0, $a0, 1020
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -33,7 +33,7 @@ define i1 @issignaling_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 1
+; CHECK-NEXT: andi $a0, $a0, 1
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -46,7 +46,7 @@ define i1 @not_issignaling_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 1022
+; CHECK-NEXT: andi $a0, $a0, 1022
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -59,7 +59,7 @@ define i1 @isquiet_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 2
+; CHECK-NEXT: andi $a0, $a0, 2
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -72,7 +72,7 @@ define i1 @not_isquiet_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 1021
+; CHECK-NEXT: andi $a0, $a0, 1021
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -85,7 +85,7 @@ define i1 @isinf_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 68
+; CHECK-NEXT: andi $a0, $a0, 68
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -98,7 +98,7 @@ define i1 @not_isinf_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 955
+; CHECK-NEXT: andi $a0, $a0, 955
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -111,7 +111,7 @@ define i1 @is_plus_inf_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 64
+; CHECK-NEXT: andi $a0, $a0, 64
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -124,7 +124,7 @@ define i1 @is_minus_inf_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 4
+; CHECK-NEXT: andi $a0, $a0, 4
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -137,7 +137,7 @@ define i1 @not_is_minus_inf_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 1019
+; CHECK-NEXT: andi $a0, $a0, 1019
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -150,7 +150,7 @@ define i1 @isfinite_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 952
+; CHECK-NEXT: andi $a0, $a0, 952
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -163,7 +163,7 @@ define i1 @not_isfinite_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 71
+; CHECK-NEXT: andi $a0, $a0, 71
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -176,7 +176,7 @@ define i1 @is_plus_finite_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 896
+; CHECK-NEXT: andi $a0, $a0, 896
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -189,7 +189,7 @@ define i1 @not_is_plus_finite_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 127
+; CHECK-NEXT: andi $a0, $a0, 127
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -202,7 +202,7 @@ define i1 @is_minus_finite_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 56
+; CHECK-NEXT: andi $a0, $a0, 56
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -215,7 +215,7 @@ define i1 @not_is_minus_finite_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 967
+; CHECK-NEXT: andi $a0, $a0, 967
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -228,7 +228,7 @@ define i1 @isnormal_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 136
+; CHECK-NEXT: andi $a0, $a0, 136
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -241,7 +241,7 @@ define i1 @not_isnormal_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 887
+; CHECK-NEXT: andi $a0, $a0, 887
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -254,7 +254,7 @@ define i1 @is_plus_normal_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 128
+; CHECK-NEXT: andi $a0, $a0, 128
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -267,7 +267,7 @@ define i1 @issubnormal_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 272
+; CHECK-NEXT: andi $a0, $a0, 272
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -280,7 +280,7 @@ define i1 @not_issubnormal_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 751
+; CHECK-NEXT: andi $a0, $a0, 751
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -293,7 +293,7 @@ define i1 @is_plus_subnormal_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 256
+; CHECK-NEXT: andi $a0, $a0, 256
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -306,7 +306,7 @@ define i1 @not_is_plus_subnormal_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 767
+; CHECK-NEXT: andi $a0, $a0, 767
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -319,7 +319,7 @@ define i1 @is_minus_subnormal_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 16
+; CHECK-NEXT: andi $a0, $a0, 16
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -332,7 +332,7 @@ define i1 @not_is_minus_subnormal_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 1007
+; CHECK-NEXT: andi $a0, $a0, 1007
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -345,7 +345,7 @@ define i1 @iszero_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 544
+; CHECK-NEXT: andi $a0, $a0, 544
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -358,7 +358,7 @@ define i1 @not_iszero_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 479
+; CHECK-NEXT: andi $a0, $a0, 479
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -371,7 +371,7 @@ define i1 @issubnormal_or_zero_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 816
+; CHECK-NEXT: andi $a0, $a0, 816
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -384,7 +384,7 @@ define i1 @not_issubnormal_or_zero_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 207
+; CHECK-NEXT: andi $a0, $a0, 207
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -397,7 +397,7 @@ define i1 @is_plus_zero_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 512
+; CHECK-NEXT: andi $a0, $a0, 512
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -410,7 +410,7 @@ define i1 @not_is_plus_zero_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 511
+; CHECK-NEXT: andi $a0, $a0, 511
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -423,7 +423,7 @@ define i1 @is_minus_zero_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 32
+; CHECK-NEXT: andi $a0, $a0, 32
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -436,7 +436,7 @@ define i1 @not_is_minus_zero_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 991
+; CHECK-NEXT: andi $a0, $a0, 991
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -449,7 +449,7 @@ define i1 @isnone_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 0
+; CHECK-NEXT: andi $a0, $a0, 0
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -462,7 +462,7 @@ define i1 @isany_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 1023
+; CHECK-NEXT: andi $a0, $a0, 1023
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -475,7 +475,7 @@ define i1 @iszero_or_nan_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 547
+; CHECK-NEXT: andi $a0, $a0, 547
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -488,7 +488,7 @@ define i1 @not_iszero_or_nan_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 476
+; CHECK-NEXT: andi $a0, $a0, 476
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -501,7 +501,7 @@ define i1 @iszero_or_qnan_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 546
+; CHECK-NEXT: andi $a0, $a0, 546
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -514,7 +514,7 @@ define i1 @iszero_or_snan_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 545
+; CHECK-NEXT: andi $a0, $a0, 545
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -527,7 +527,7 @@ define i1 @not_iszero_or_qnan_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 477
+; CHECK-NEXT: andi $a0, $a0, 477
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -540,7 +540,7 @@ define i1 @not_iszero_or_snan_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 478
+; CHECK-NEXT: andi $a0, $a0, 478
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -553,7 +553,7 @@ define i1 @isinf_or_nan_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 71
+; CHECK-NEXT: andi $a0, $a0, 71
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -566,7 +566,7 @@ define i1 @not_isinf_or_nan_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 952
+; CHECK-NEXT: andi $a0, $a0, 952
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -579,7 +579,7 @@ define i1 @isfinite_or_nan_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 955
+; CHECK-NEXT: andi $a0, $a0, 955
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -592,7 +592,7 @@ define i1 @not_isfinite_or_nan_f(float %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 68
+; CHECK-NEXT: andi $a0, $a0, 68
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
entry:
@@ -605,7 +605,7 @@ define i1 @is_plus_inf_or_nan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 67
+; CHECK-NEXT: andi $a0, $a0, 67
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 515) ; 0x200|0x3 = "+inf|nan"
@@ -617,7 +617,7 @@ define i1 @is_minus_inf_or_nan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 7
+; CHECK-NEXT: andi $a0, $a0, 7
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 7) ; "-inf|nan"
@@ -629,7 +629,7 @@ define i1 @not_is_plus_inf_or_nan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 956
+; CHECK-NEXT: andi $a0, $a0, 956
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 508) ; ~(0x200|0x3) = "~(+inf|nan)"
@@ -641,7 +641,7 @@ define i1 @not_is_minus_inf_or_nan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 1016
+; CHECK-NEXT: andi $a0, $a0, 1016
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1016) ; "~(-inf|nan)"
@@ -653,7 +653,7 @@ define i1 @is_plus_inf_or_snan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 65
+; CHECK-NEXT: andi $a0, $a0, 65
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 513) ; 0x200|0x1 = "+inf|snan"
@@ -665,7 +665,7 @@ define i1 @is_plus_inf_or_qnan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 66
+; CHECK-NEXT: andi $a0, $a0, 66
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 514) ; 0x200|0x1 = "+inf|qnan"
@@ -677,7 +677,7 @@ define i1 @not_is_plus_inf_or_snan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 958
+; CHECK-NEXT: andi $a0, $a0, 958
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 510) ; ~(+inf|snan)
@@ -689,7 +689,7 @@ define i1 @not_is_plus_inf_or_qnan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 957
+; CHECK-NEXT: andi $a0, $a0, 957
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 509) ; ~(+inf|qnan)
@@ -701,7 +701,7 @@ define i1 @is_minus_inf_or_snan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 5
+; CHECK-NEXT: andi $a0, $a0, 5
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 5) ; "-inf|snan"
@@ -713,7 +713,7 @@ define i1 @is_minus_inf_or_qnan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 6
+; CHECK-NEXT: andi $a0, $a0, 6
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 6) ; "-inf|qnan"
@@ -725,7 +725,7 @@ define i1 @not_is_minus_inf_or_snan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 1018
+; CHECK-NEXT: andi $a0, $a0, 1018
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1018) ; "~(-inf|snan)"
@@ -737,7 +737,7 @@ define i1 @not_is_minus_inf_or_qnan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 1017
+; CHECK-NEXT: andi $a0, $a0, 1017
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1017) ; "-inf|qnan"
@@ -749,7 +749,7 @@ define i1 @issubnormal_or_nan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 275
+; CHECK-NEXT: andi $a0, $a0, 275
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 147) ; 0x90|0x3 = "subnormal|nan"
@@ -761,7 +761,7 @@ define i1 @issubnormal_or_zero_or_nan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 819
+; CHECK-NEXT: andi $a0, $a0, 819
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 243) ; 0xf0|0x3 = "subnormal|zero|nan"
@@ -773,7 +773,7 @@ define i1 @issubnormal_or_zero_or_snan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 817
+; CHECK-NEXT: andi $a0, $a0, 817
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 241) ; 0x90|0x1 = "subnormal|snan"
@@ -785,7 +785,7 @@ define i1 @issubnormal_or_zero_or_qnan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 818
+; CHECK-NEXT: andi $a0, $a0, 818
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 242) ; 0x90|0x2 = "subnormal|qnan"
@@ -797,7 +797,7 @@ define i1 @not_issubnormal_or_nan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 748
+; CHECK-NEXT: andi $a0, $a0, 748
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 876) ; ~(0x90|0x3) = ~"subnormal|nan"
@@ -809,7 +809,7 @@ define i1 @not_issubnormal_or_zero_or_nan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 204
+; CHECK-NEXT: andi $a0, $a0, 204
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 780) ; ~(0xf0|0x3) = ~"subnormal|zero|nan"
@@ -821,7 +821,7 @@ define i1 @not_issubnormal_or_zero_or_snan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 206
+; CHECK-NEXT: andi $a0, $a0, 206
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 782) ; ~(0x90|0x1) = ~"subnormal|snan"
@@ -833,7 +833,7 @@ define i1 @not_issubnormal_or_zero_or_qnan_f(float %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: fclass.s $fa0, $fa0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
-; CHECK-NEXT: and $a0, $a0, 205
+; CHECK-NEXT: andi $a0, $a0, 205
; CHECK-NEXT: sltu $a0, $zero, $a0
; CHECK-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 781) ; ~(0x90|0x2) = ~"subnormal|qnan"
diff --git a/llvm/test/CodeGen/LoongArch/is_fpclass_f64.ll b/llvm/test/CodeGen/LoongArch/is_fpclass_f64.ll
index 590e1db84b14af4..e58f81a08e4c575 100644
--- a/llvm/test/CodeGen/LoongArch/is_fpclass_f64.ll
+++ b/llvm/test/CodeGen/LoongArch/is_fpclass_f64.ll
@@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=CHECK32
-; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=CHECK64
+; RUN: llc --mtriple=loongarch32 --mattr=+d --verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK32
+; RUN: llc --mtriple=loongarch64 --mattr=+d --verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK64
define i1 @isnan_d(double %x) {
; CHECK32-LABEL: isnan_d:
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 3
+; CHECK32-NEXT: andi $a0, $a0, 3
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -15,7 +15,7 @@ define i1 @isnan_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 3
+; CHECK64-NEXT: andi $a0, $a0, 3
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -28,7 +28,7 @@ define i1 @isnot_nan_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 1020
+; CHECK32-NEXT: andi $a0, $a0, 1020
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -36,7 +36,7 @@ define i1 @isnot_nan_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 1020
+; CHECK64-NEXT: andi $a0, $a0, 1020
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -49,7 +49,7 @@ define i1 @issignaling_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 1
+; CHECK32-NEXT: andi $a0, $a0, 1
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -57,7 +57,7 @@ define i1 @issignaling_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 1
+; CHECK64-NEXT: andi $a0, $a0, 1
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -70,7 +70,7 @@ define i1 @not_issignaling_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 1022
+; CHECK32-NEXT: andi $a0, $a0, 1022
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -78,7 +78,7 @@ define i1 @not_issignaling_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 1022
+; CHECK64-NEXT: andi $a0, $a0, 1022
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -91,7 +91,7 @@ define i1 @isquiet_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 2
+; CHECK32-NEXT: andi $a0, $a0, 2
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -99,7 +99,7 @@ define i1 @isquiet_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 2
+; CHECK64-NEXT: andi $a0, $a0, 2
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -112,7 +112,7 @@ define i1 @not_isquiet_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 1021
+; CHECK32-NEXT: andi $a0, $a0, 1021
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -120,7 +120,7 @@ define i1 @not_isquiet_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 1021
+; CHECK64-NEXT: andi $a0, $a0, 1021
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -133,7 +133,7 @@ define i1 @isinf_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 68
+; CHECK32-NEXT: andi $a0, $a0, 68
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -141,7 +141,7 @@ define i1 @isinf_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 68
+; CHECK64-NEXT: andi $a0, $a0, 68
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -154,7 +154,7 @@ define i1 @not_isinf_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 955
+; CHECK32-NEXT: andi $a0, $a0, 955
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -162,7 +162,7 @@ define i1 @not_isinf_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 955
+; CHECK64-NEXT: andi $a0, $a0, 955
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -175,7 +175,7 @@ define i1 @is_plus_inf_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 64
+; CHECK32-NEXT: andi $a0, $a0, 64
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -183,7 +183,7 @@ define i1 @is_plus_inf_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 64
+; CHECK64-NEXT: andi $a0, $a0, 64
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -196,7 +196,7 @@ define i1 @is_minus_inf_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 4
+; CHECK32-NEXT: andi $a0, $a0, 4
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -204,7 +204,7 @@ define i1 @is_minus_inf_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 4
+; CHECK64-NEXT: andi $a0, $a0, 4
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -217,7 +217,7 @@ define i1 @not_is_minus_inf_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 1019
+; CHECK32-NEXT: andi $a0, $a0, 1019
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -225,7 +225,7 @@ define i1 @not_is_minus_inf_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 1019
+; CHECK64-NEXT: andi $a0, $a0, 1019
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -238,7 +238,7 @@ define i1 @isfinite_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 952
+; CHECK32-NEXT: andi $a0, $a0, 952
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -246,7 +246,7 @@ define i1 @isfinite_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 952
+; CHECK64-NEXT: andi $a0, $a0, 952
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -259,7 +259,7 @@ define i1 @not_isfinite_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 71
+; CHECK32-NEXT: andi $a0, $a0, 71
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -267,7 +267,7 @@ define i1 @not_isfinite_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 71
+; CHECK64-NEXT: andi $a0, $a0, 71
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -280,7 +280,7 @@ define i1 @is_plus_finite_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 896
+; CHECK32-NEXT: andi $a0, $a0, 896
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -288,7 +288,7 @@ define i1 @is_plus_finite_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 896
+; CHECK64-NEXT: andi $a0, $a0, 896
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -301,7 +301,7 @@ define i1 @not_is_plus_finite_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 127
+; CHECK32-NEXT: andi $a0, $a0, 127
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -309,7 +309,7 @@ define i1 @not_is_plus_finite_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 127
+; CHECK64-NEXT: andi $a0, $a0, 127
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -322,7 +322,7 @@ define i1 @is_minus_finite_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 56
+; CHECK32-NEXT: andi $a0, $a0, 56
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -330,7 +330,7 @@ define i1 @is_minus_finite_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 56
+; CHECK64-NEXT: andi $a0, $a0, 56
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -343,7 +343,7 @@ define i1 @not_is_minus_finite_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 967
+; CHECK32-NEXT: andi $a0, $a0, 967
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -351,7 +351,7 @@ define i1 @not_is_minus_finite_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 967
+; CHECK64-NEXT: andi $a0, $a0, 967
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -364,7 +364,7 @@ define i1 @isnormal_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 136
+; CHECK32-NEXT: andi $a0, $a0, 136
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -372,7 +372,7 @@ define i1 @isnormal_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 136
+; CHECK64-NEXT: andi $a0, $a0, 136
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -385,7 +385,7 @@ define i1 @not_isnormal_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 887
+; CHECK32-NEXT: andi $a0, $a0, 887
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -393,7 +393,7 @@ define i1 @not_isnormal_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 887
+; CHECK64-NEXT: andi $a0, $a0, 887
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -406,7 +406,7 @@ define i1 @is_plus_normal_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 128
+; CHECK32-NEXT: andi $a0, $a0, 128
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -414,7 +414,7 @@ define i1 @is_plus_normal_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 128
+; CHECK64-NEXT: andi $a0, $a0, 128
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -427,7 +427,7 @@ define i1 @issubnormal_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 272
+; CHECK32-NEXT: andi $a0, $a0, 272
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -435,7 +435,7 @@ define i1 @issubnormal_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 272
+; CHECK64-NEXT: andi $a0, $a0, 272
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -448,7 +448,7 @@ define i1 @not_issubnormal_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 751
+; CHECK32-NEXT: andi $a0, $a0, 751
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -456,7 +456,7 @@ define i1 @not_issubnormal_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 751
+; CHECK64-NEXT: andi $a0, $a0, 751
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -469,7 +469,7 @@ define i1 @is_plus_subnormal_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 256
+; CHECK32-NEXT: andi $a0, $a0, 256
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -477,7 +477,7 @@ define i1 @is_plus_subnormal_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 256
+; CHECK64-NEXT: andi $a0, $a0, 256
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -490,7 +490,7 @@ define i1 @not_is_plus_subnormal_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 767
+; CHECK32-NEXT: andi $a0, $a0, 767
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -498,7 +498,7 @@ define i1 @not_is_plus_subnormal_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 767
+; CHECK64-NEXT: andi $a0, $a0, 767
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -511,7 +511,7 @@ define i1 @is_minus_subnormal_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 16
+; CHECK32-NEXT: andi $a0, $a0, 16
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -519,7 +519,7 @@ define i1 @is_minus_subnormal_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 16
+; CHECK64-NEXT: andi $a0, $a0, 16
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -532,7 +532,7 @@ define i1 @not_is_minus_subnormal_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 1007
+; CHECK32-NEXT: andi $a0, $a0, 1007
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -540,7 +540,7 @@ define i1 @not_is_minus_subnormal_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 1007
+; CHECK64-NEXT: andi $a0, $a0, 1007
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -553,7 +553,7 @@ define i1 @iszero_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 544
+; CHECK32-NEXT: andi $a0, $a0, 544
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -561,7 +561,7 @@ define i1 @iszero_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 544
+; CHECK64-NEXT: andi $a0, $a0, 544
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -574,7 +574,7 @@ define i1 @not_iszero_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 479
+; CHECK32-NEXT: andi $a0, $a0, 479
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -582,7 +582,7 @@ define i1 @not_iszero_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 479
+; CHECK64-NEXT: andi $a0, $a0, 479
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -595,7 +595,7 @@ define i1 @issubnormal_or_zero_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 816
+; CHECK32-NEXT: andi $a0, $a0, 816
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -603,7 +603,7 @@ define i1 @issubnormal_or_zero_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 816
+; CHECK64-NEXT: andi $a0, $a0, 816
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -616,7 +616,7 @@ define i1 @not_issubnormal_or_zero_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 207
+; CHECK32-NEXT: andi $a0, $a0, 207
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -624,7 +624,7 @@ define i1 @not_issubnormal_or_zero_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 207
+; CHECK64-NEXT: andi $a0, $a0, 207
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -637,7 +637,7 @@ define i1 @is_plus_zero_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 512
+; CHECK32-NEXT: andi $a0, $a0, 512
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -645,7 +645,7 @@ define i1 @is_plus_zero_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 512
+; CHECK64-NEXT: andi $a0, $a0, 512
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -658,7 +658,7 @@ define i1 @not_is_plus_zero_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 511
+; CHECK32-NEXT: andi $a0, $a0, 511
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -666,7 +666,7 @@ define i1 @not_is_plus_zero_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 511
+; CHECK64-NEXT: andi $a0, $a0, 511
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -679,7 +679,7 @@ define i1 @is_minus_zero_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 32
+; CHECK32-NEXT: andi $a0, $a0, 32
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -687,7 +687,7 @@ define i1 @is_minus_zero_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 32
+; CHECK64-NEXT: andi $a0, $a0, 32
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -700,7 +700,7 @@ define i1 @not_is_minus_zero_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 991
+; CHECK32-NEXT: andi $a0, $a0, 991
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -708,7 +708,7 @@ define i1 @not_is_minus_zero_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 991
+; CHECK64-NEXT: andi $a0, $a0, 991
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -721,7 +721,7 @@ define i1 @isnone_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 0
+; CHECK32-NEXT: andi $a0, $a0, 0
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -729,7 +729,7 @@ define i1 @isnone_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 0
+; CHECK64-NEXT: andi $a0, $a0, 0
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -742,7 +742,7 @@ define i1 @isany_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 1023
+; CHECK32-NEXT: andi $a0, $a0, 1023
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -750,7 +750,7 @@ define i1 @isany_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 1023
+; CHECK64-NEXT: andi $a0, $a0, 1023
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -763,7 +763,7 @@ define i1 @iszero_or_nan_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 547
+; CHECK32-NEXT: andi $a0, $a0, 547
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -771,7 +771,7 @@ define i1 @iszero_or_nan_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 547
+; CHECK64-NEXT: andi $a0, $a0, 547
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -784,7 +784,7 @@ define i1 @not_iszero_or_nan_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 476
+; CHECK32-NEXT: andi $a0, $a0, 476
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -792,7 +792,7 @@ define i1 @not_iszero_or_nan_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 476
+; CHECK64-NEXT: andi $a0, $a0, 476
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -805,7 +805,7 @@ define i1 @iszero_or_qnan_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 546
+; CHECK32-NEXT: andi $a0, $a0, 546
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -813,7 +813,7 @@ define i1 @iszero_or_qnan_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 546
+; CHECK64-NEXT: andi $a0, $a0, 546
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -826,7 +826,7 @@ define i1 @iszero_or_snan_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 545
+; CHECK32-NEXT: andi $a0, $a0, 545
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -834,7 +834,7 @@ define i1 @iszero_or_snan_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 545
+; CHECK64-NEXT: andi $a0, $a0, 545
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -847,7 +847,7 @@ define i1 @not_iszero_or_qnan_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 477
+; CHECK32-NEXT: andi $a0, $a0, 477
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -855,7 +855,7 @@ define i1 @not_iszero_or_qnan_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 477
+; CHECK64-NEXT: andi $a0, $a0, 477
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -868,7 +868,7 @@ define i1 @not_iszero_or_snan_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 478
+; CHECK32-NEXT: andi $a0, $a0, 478
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -876,7 +876,7 @@ define i1 @not_iszero_or_snan_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 478
+; CHECK64-NEXT: andi $a0, $a0, 478
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -889,7 +889,7 @@ define i1 @isinf_or_nan_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 71
+; CHECK32-NEXT: andi $a0, $a0, 71
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -897,7 +897,7 @@ define i1 @isinf_or_nan_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 71
+; CHECK64-NEXT: andi $a0, $a0, 71
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -910,7 +910,7 @@ define i1 @not_isinf_or_nan_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 952
+; CHECK32-NEXT: andi $a0, $a0, 952
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -918,7 +918,7 @@ define i1 @not_isinf_or_nan_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 952
+; CHECK64-NEXT: andi $a0, $a0, 952
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -931,7 +931,7 @@ define i1 @isfinite_or_nan_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 955
+; CHECK32-NEXT: andi $a0, $a0, 955
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -939,7 +939,7 @@ define i1 @isfinite_or_nan_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 955
+; CHECK64-NEXT: andi $a0, $a0, 955
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -952,7 +952,7 @@ define i1 @not_isfinite_or_nan_d(double %x) {
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 68
+; CHECK32-NEXT: andi $a0, $a0, 68
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -960,7 +960,7 @@ define i1 @not_isfinite_or_nan_d(double %x) {
; CHECK64: # %bb.0: # %entry
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 68
+; CHECK64-NEXT: andi $a0, $a0, 68
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
entry:
@@ -973,7 +973,7 @@ define i1 @is_plus_inf_or_nan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 67
+; CHECK32-NEXT: andi $a0, $a0, 67
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -981,7 +981,7 @@ define i1 @is_plus_inf_or_nan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 67
+; CHECK64-NEXT: andi $a0, $a0, 67
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 515) ; 0x200|0x3 = "+inf|nan"
@@ -993,7 +993,7 @@ define i1 @is_minus_inf_or_nan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 7
+; CHECK32-NEXT: andi $a0, $a0, 7
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1001,7 +1001,7 @@ define i1 @is_minus_inf_or_nan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 7
+; CHECK64-NEXT: andi $a0, $a0, 7
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 7) ; "-inf|nan"
@@ -1013,7 +1013,7 @@ define i1 @not_is_plus_inf_or_nan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 956
+; CHECK32-NEXT: andi $a0, $a0, 956
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1021,7 +1021,7 @@ define i1 @not_is_plus_inf_or_nan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 956
+; CHECK64-NEXT: andi $a0, $a0, 956
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 508) ; ~(0x200|0x3) = "~(+inf|nan)"
@@ -1033,7 +1033,7 @@ define i1 @not_is_minus_inf_or_nan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 1016
+; CHECK32-NEXT: andi $a0, $a0, 1016
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1041,7 +1041,7 @@ define i1 @not_is_minus_inf_or_nan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 1016
+; CHECK64-NEXT: andi $a0, $a0, 1016
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1016) ; "~(-inf|nan)"
@@ -1053,7 +1053,7 @@ define i1 @is_plus_inf_or_snan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 65
+; CHECK32-NEXT: andi $a0, $a0, 65
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1061,7 +1061,7 @@ define i1 @is_plus_inf_or_snan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 65
+; CHECK64-NEXT: andi $a0, $a0, 65
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 513) ; 0x200|0x1 = "+inf|snan"
@@ -1073,7 +1073,7 @@ define i1 @is_plus_inf_or_qnan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 66
+; CHECK32-NEXT: andi $a0, $a0, 66
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1081,7 +1081,7 @@ define i1 @is_plus_inf_or_qnan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 66
+; CHECK64-NEXT: andi $a0, $a0, 66
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 514) ; 0x200|0x1 = "+inf|qnan"
@@ -1093,7 +1093,7 @@ define i1 @not_is_plus_inf_or_snan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 958
+; CHECK32-NEXT: andi $a0, $a0, 958
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1101,7 +1101,7 @@ define i1 @not_is_plus_inf_or_snan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 958
+; CHECK64-NEXT: andi $a0, $a0, 958
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 510) ; ~(+inf|snan)
@@ -1113,7 +1113,7 @@ define i1 @not_is_plus_inf_or_qnan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 957
+; CHECK32-NEXT: andi $a0, $a0, 957
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1121,7 +1121,7 @@ define i1 @not_is_plus_inf_or_qnan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 957
+; CHECK64-NEXT: andi $a0, $a0, 957
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 509) ; ~(+inf|qnan)
@@ -1133,7 +1133,7 @@ define i1 @is_minus_inf_or_snan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 5
+; CHECK32-NEXT: andi $a0, $a0, 5
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1141,7 +1141,7 @@ define i1 @is_minus_inf_or_snan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 5
+; CHECK64-NEXT: andi $a0, $a0, 5
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 5) ; "-inf|snan"
@@ -1153,7 +1153,7 @@ define i1 @is_minus_inf_or_qnan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 6
+; CHECK32-NEXT: andi $a0, $a0, 6
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1161,7 +1161,7 @@ define i1 @is_minus_inf_or_qnan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 6
+; CHECK64-NEXT: andi $a0, $a0, 6
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 6) ; "-inf|qnan"
@@ -1173,7 +1173,7 @@ define i1 @not_is_minus_inf_or_snan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 1018
+; CHECK32-NEXT: andi $a0, $a0, 1018
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1181,7 +1181,7 @@ define i1 @not_is_minus_inf_or_snan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 1018
+; CHECK64-NEXT: andi $a0, $a0, 1018
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1018) ; "~(-inf|snan)"
@@ -1193,7 +1193,7 @@ define i1 @not_is_minus_inf_or_qnan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 1017
+; CHECK32-NEXT: andi $a0, $a0, 1017
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1201,7 +1201,7 @@ define i1 @not_is_minus_inf_or_qnan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 1017
+; CHECK64-NEXT: andi $a0, $a0, 1017
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1017) ; "-inf|qnan"
@@ -1213,7 +1213,7 @@ define i1 @issubnormal_or_nan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 275
+; CHECK32-NEXT: andi $a0, $a0, 275
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1221,7 +1221,7 @@ define i1 @issubnormal_or_nan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 275
+; CHECK64-NEXT: andi $a0, $a0, 275
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 147) ; 0x90|0x3 = "subnormal|nan"
@@ -1233,7 +1233,7 @@ define i1 @issubnormal_or_zero_or_nan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 819
+; CHECK32-NEXT: andi $a0, $a0, 819
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1241,7 +1241,7 @@ define i1 @issubnormal_or_zero_or_nan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 819
+; CHECK64-NEXT: andi $a0, $a0, 819
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 243) ; 0xf0|0x3 = "subnormal|zero|nan"
@@ -1253,7 +1253,7 @@ define i1 @issubnormal_or_zero_or_snan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 817
+; CHECK32-NEXT: andi $a0, $a0, 817
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1261,7 +1261,7 @@ define i1 @issubnormal_or_zero_or_snan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 817
+; CHECK64-NEXT: andi $a0, $a0, 817
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 241) ; 0x90|0x1 = "subnormal|snan"
@@ -1273,7 +1273,7 @@ define i1 @issubnormal_or_zero_or_qnan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 818
+; CHECK32-NEXT: andi $a0, $a0, 818
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1281,7 +1281,7 @@ define i1 @issubnormal_or_zero_or_qnan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 818
+; CHECK64-NEXT: andi $a0, $a0, 818
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 242) ; 0x90|0x2 = "subnormal|qnan"
@@ -1293,7 +1293,7 @@ define i1 @not_issubnormal_or_nan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 748
+; CHECK32-NEXT: andi $a0, $a0, 748
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1301,7 +1301,7 @@ define i1 @not_issubnormal_or_nan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 748
+; CHECK64-NEXT: andi $a0, $a0, 748
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 876) ; ~(0x90|0x3) = ~"subnormal|nan"
@@ -1313,7 +1313,7 @@ define i1 @not_issubnormal_or_zero_or_nan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 204
+; CHECK32-NEXT: andi $a0, $a0, 204
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1321,7 +1321,7 @@ define i1 @not_issubnormal_or_zero_or_nan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 204
+; CHECK64-NEXT: andi $a0, $a0, 204
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 780) ; ~(0xf0|0x3) = ~"subnormal|zero|nan"
@@ -1333,7 +1333,7 @@ define i1 @not_issubnormal_or_zero_or_snan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 206
+; CHECK32-NEXT: andi $a0, $a0, 206
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1341,7 +1341,7 @@ define i1 @not_issubnormal_or_zero_or_snan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 206
+; CHECK64-NEXT: andi $a0, $a0, 206
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 782) ; ~(0x90|0x1) = ~"subnormal|snan"
@@ -1353,7 +1353,7 @@ define i1 @not_issubnormal_or_zero_or_qnan_d(double %x) {
; CHECK32: # %bb.0:
; CHECK32-NEXT: fclass.d $fa0, $fa0
; CHECK32-NEXT: movfr2gr.s $a0, $fa0
-; CHECK32-NEXT: and $a0, $a0, 205
+; CHECK32-NEXT: andi $a0, $a0, 205
; CHECK32-NEXT: sltu $a0, $zero, $a0
; CHECK32-NEXT: ret
;
@@ -1361,7 +1361,7 @@ define i1 @not_issubnormal_or_zero_or_qnan_d(double %x) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: fclass.d $fa0, $fa0
; CHECK64-NEXT: movfr2gr.d $a0, $fa0
-; CHECK64-NEXT: and $a0, $a0, 205
+; CHECK64-NEXT: andi $a0, $a0, 205
; CHECK64-NEXT: sltu $a0, $zero, $a0
; CHECK64-NEXT: ret
%class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 781) ; ~(0x90|0x2) = ~"subnormal|qnan"
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