[llvm] [DX] Support pipeline state masks (PR #66425)
Chris B via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 14 12:43:50 PDT 2023
https://github.com/llvm-beanz created https://github.com/llvm/llvm-project/pull/66425:
The DXContainer pipeline state information encodes a bunch of mask vectors that are used to track things about the inputs and outputs from each shader.
This adds support for reading and writing them throught he YAML test interfaces. The writing logic in MC is extremely primitive and we'll want to revisit the API for that, but since I'm not sure how we'll want to generate the mask bits from DXIL during code generation I didn't want to spend too much time on the API.
Fixes #59479
>From 0b13ef6634459587dbb97b3c905b89d3f10723a9 Mon Sep 17 00:00:00 2001
From: Chris Bieneman <chris.bieneman at me.com>
Date: Thu, 14 Sep 2023 14:36:07 -0500
Subject: [PATCH] [DX] Support pipeline state masks
The DXContainer pipeline state information encodes a bunch of mask
vectors that are used to track things about the inputs and outputs from
each shader.
This adds support for reading and writing them throught he YAML test
interfaces. The writing logic in MC is extremely primitive and we'll
want to revisit the API for that, but since I'm not sure how we'll want
to generate the mask bits from DXIL during code generation I didn't
want to spend too much time on the API.
---
llvm/include/llvm/MC/DXContainerPSVInfo.h | 12 ++
llvm/include/llvm/Object/DXContainer.h | 77 ++++++-
.../include/llvm/ObjectYAML/DXContainerYAML.h | 8 +
llvm/include/llvm/Support/EndianStream.h | 9 +
llvm/lib/MC/DXContainerPSVInfo.cpp | 13 ++
llvm/lib/Object/DXContainer.cpp | 62 ++++++
llvm/lib/ObjectYAML/DXContainerEmitter.cpp | 19 ++
llvm/lib/ObjectYAML/DXContainerYAML.cpp | 18 ++
.../DXContainer/DomainMaskVectors.yaml | 200 ++++++++++++++++++
.../DXContainer/GeometryMaskVectors.yaml | 174 +++++++++++++++
.../DXContainer/HullMaskVectors.yaml | 181 ++++++++++++++++
.../DXContainer/PSVv1-amplification.yaml | 18 +-
.../ObjectYAML/DXContainer/PSVv1-compute.yaml | 18 +-
.../ObjectYAML/DXContainer/PSVv1-domain.yaml | 28 ++-
.../DXContainer/PSVv1-geometry.yaml | 18 +-
.../ObjectYAML/DXContainer/PSVv1-hull.yaml | 28 ++-
.../ObjectYAML/DXContainer/PSVv1-mesh.yaml | 18 +-
.../ObjectYAML/DXContainer/PSVv1-pixel.yaml | 18 +-
.../ObjectYAML/DXContainer/PSVv1-vertex.yaml | 18 +-
.../DXContainer/PSVv2-amplification.yaml | 18 +-
.../ObjectYAML/DXContainer/PSVv2-compute.yaml | 18 +-
.../ObjectYAML/DXContainer/PSVv2-domain.yaml | 28 ++-
.../DXContainer/PSVv2-geometry.yaml | 18 +-
.../ObjectYAML/DXContainer/PSVv2-hull.yaml | 28 ++-
.../ObjectYAML/DXContainer/PSVv2-mesh.yaml | 18 +-
.../ObjectYAML/DXContainer/PSVv2-pixel.yaml | 18 +-
.../ObjectYAML/DXContainer/PSVv2-vertex.yaml | 18 +-
.../ObjectYAML/DXContainer/SigElements.yaml | 9 +-
llvm/tools/obj2yaml/dxcontainer2yaml.cpp | 19 ++
29 files changed, 1045 insertions(+), 84 deletions(-)
create mode 100644 llvm/test/ObjectYAML/DXContainer/DomainMaskVectors.yaml
create mode 100644 llvm/test/ObjectYAML/DXContainer/GeometryMaskVectors.yaml
create mode 100644 llvm/test/ObjectYAML/DXContainer/HullMaskVectors.yaml
diff --git a/llvm/include/llvm/MC/DXContainerPSVInfo.h b/llvm/include/llvm/MC/DXContainerPSVInfo.h
index dc6bf2fa40d065a..76e3e498029c4a1 100644
--- a/llvm/include/llvm/MC/DXContainerPSVInfo.h
+++ b/llvm/include/llvm/MC/DXContainerPSVInfo.h
@@ -51,6 +51,18 @@ struct PSVRuntimeInfo {
SmallVector<PSVSignatureElement> OutputElements;
SmallVector<PSVSignatureElement> PatchOrPrimElements;
+ // The interface here is bad, and we'll want to change this in the future. We
+ // probably will want to build out these mask vectors as vectors of bools and
+ // have this utility object convert them to the bit masks. I don't want to
+ // over-engineer this API now since we don't know what the data coming in to
+ // feed it will look like, so I kept it extremely simple for the immediate use
+ // case.
+ SmallVector<uint32_t> OutputVectorMasks[4];
+ SmallVector<uint32_t> PatchOrPrimMasks;
+ SmallVector<uint32_t> InputOutputMap[4];
+ SmallVector<uint32_t> InputPatchMap;
+ SmallVector<uint32_t> PatchOutputMap;
+
// Serialize PSVInfo into the provided raw_ostream. The version field
// specifies the data version to encode, the default value specifies encoding
// the highest supported version.
diff --git a/llvm/include/llvm/Object/DXContainer.h b/llvm/include/llvm/Object/DXContainer.h
index 2aae0a199f8c1c0..9ea8a48f9430d74 100644
--- a/llvm/include/llvm/Object/DXContainer.h
+++ b/llvm/include/llvm/Object/DXContainer.h
@@ -27,6 +27,18 @@ namespace llvm {
namespace object {
namespace DirectX {
+
+namespace detail {
+template <typename T>
+std::enable_if_t<std::is_arithmetic<T>::value, void> swapBytes(T &value) {
+ sys::swapByteOrder(value);
+}
+
+template <typename T>
+std::enable_if_t<std::is_class<T>::value, void> swapBytes(T &value) {
+ value.swapBytes();
+}
+} // namespace detail
class PSVRuntimeInfo {
// This class provides a view into the underlying resource array. The Resource
@@ -35,7 +47,7 @@ class PSVRuntimeInfo {
// swaps it as appropriate.
template <typename T> struct ViewArray {
StringRef Data;
- uint32_t Stride; // size of each element in the list.
+ uint32_t Stride = sizeof(T); // size of each element in the list.
ViewArray() = default;
ViewArray(StringRef D, size_t S) : Data(D), Stride(S) {}
@@ -65,7 +77,7 @@ class PSVRuntimeInfo {
memcpy(static_cast<void *>(&Val), Current,
std::min(Stride, MaxStride()));
if (sys::IsBigEndianHost)
- Val.swapBytes();
+ detail::swapBytes(Val);
return Val;
}
@@ -120,6 +132,12 @@ class PSVRuntimeInfo {
SigElementArray SigOutputElements;
SigElementArray SigPatchOrPrimElements;
+ ViewArray<uint32_t> OutputVectorMasks[4];
+ ViewArray<uint32_t> PatchOrPrimMasks;
+ ViewArray<uint32_t> InputOutputMap[4];
+ ViewArray<uint32_t> InputPatchMap;
+ ViewArray<uint32_t> PatchOutputMap;
+
public:
PSVRuntimeInfo(StringRef D) : Data(D), Size(0) {}
@@ -140,6 +158,22 @@ class PSVRuntimeInfo {
const InfoStruct &getInfo() const { return BasicInfo; }
+ template <typename T> const T *getInfoAs() const {
+ if (const auto *P = std::get_if<dxbc::PSV::v2::RuntimeInfo>(&BasicInfo))
+ return static_cast<const T *>(P);
+ if (std::is_same<T, dxbc::PSV::v2::RuntimeInfo>::value)
+ return nullptr;
+
+ if (const auto *P = std::get_if<dxbc::PSV::v1::RuntimeInfo>(&BasicInfo))
+ return static_cast<const T *>(P);
+ if (std::is_same<T, dxbc::PSV::v1::RuntimeInfo>::value)
+ return nullptr;
+
+ if (const auto *P = std::get_if<dxbc::PSV::v0::RuntimeInfo>(&BasicInfo))
+ return static_cast<const T *>(P);
+ return nullptr;
+ }
+
StringRef getStringTable() const { return StringTable; }
ArrayRef<uint32_t> getSemanticIndexTable() const {
return SemanticIndexTable;
@@ -155,7 +189,46 @@ class PSVRuntimeInfo {
return SigPatchOrPrimElements;
}
+ ViewArray<uint32_t> getOutputVectorMasks(size_t Idx) const {
+ assert(Idx < 4);
+ return OutputVectorMasks[Idx];
+ }
+
+ ViewArray<uint32_t> getPatchOrPrimMasks() const { return PatchOrPrimMasks; }
+
+ ViewArray<uint32_t> getInputOutputMap(size_t Idx) const {
+ assert(Idx < 4);
+ return InputOutputMap[Idx];
+ }
+
+ ViewArray<uint32_t> getInputPatchMap() const { return InputPatchMap; }
+ ViewArray<uint32_t> getPatchOutputMap() const { return PatchOutputMap; }
+
uint32_t getSigElementStride() const { return SigInputElements.Stride; }
+
+ bool usesViewID() const {
+ if (const auto *P = getInfoAs<dxbc::PSV::v1::RuntimeInfo>())
+ return P->UsesViewID != 0;
+ return false;
+ }
+
+ uint8_t getInputVectorCount() const {
+ if (const auto *P = getInfoAs<dxbc::PSV::v1::RuntimeInfo>())
+ return P->SigInputVectors;
+ return 0;
+ }
+
+ ArrayRef<uint8_t> getOutputVectorCounts() const {
+ if (const auto *P = getInfoAs<dxbc::PSV::v1::RuntimeInfo>())
+ return ArrayRef<uint8_t>(P->SigOutputVectors);
+ return ArrayRef<uint8_t>();
+ }
+
+ uint8_t getPatchConstOrPrimVectorCount() const {
+ if (const auto *P = getInfoAs<dxbc::PSV::v1::RuntimeInfo>())
+ return P->GeomData.SigPatchConstOrPrimVectors;
+ return 0;
+ }
};
} // namespace DirectX
diff --git a/llvm/include/llvm/ObjectYAML/DXContainerYAML.h b/llvm/include/llvm/ObjectYAML/DXContainerYAML.h
index 1ab979fd0dfeaca..bce6fa8475bdd48 100644
--- a/llvm/include/llvm/ObjectYAML/DXContainerYAML.h
+++ b/llvm/include/llvm/ObjectYAML/DXContainerYAML.h
@@ -113,6 +113,13 @@ struct PSVInfo {
SmallVector<SignatureElement> SigOutputElements;
SmallVector<SignatureElement> SigPatchOrPrimElements;
+ using MaskVector = SmallVector<llvm::yaml::Hex32>;
+ MaskVector OutputVectorMasks[4];
+ MaskVector PatchOrPrimMasks;
+ MaskVector InputOutputMap[4];
+ MaskVector InputPatchMap;
+ MaskVector PatchOutputMap;
+
void mapInfoForVersion(yaml::IO &IO);
PSVInfo();
@@ -143,6 +150,7 @@ struct Object {
LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::DXContainerYAML::Part)
LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::DXContainerYAML::ResourceBindInfo)
LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::DXContainerYAML::SignatureElement)
+LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::DXContainerYAML::PSVInfo::MaskVector)
LLVM_YAML_DECLARE_ENUM_TRAITS(llvm::dxbc::PSV::SemanticKind)
LLVM_YAML_DECLARE_ENUM_TRAITS(llvm::dxbc::PSV::ComponentType)
LLVM_YAML_DECLARE_ENUM_TRAITS(llvm::dxbc::PSV::InterpolationMode)
diff --git a/llvm/include/llvm/Support/EndianStream.h b/llvm/include/llvm/Support/EndianStream.h
index 8ff87d23e83b145..a1dac5ad9f42a74 100644
--- a/llvm/include/llvm/Support/EndianStream.h
+++ b/llvm/include/llvm/Support/EndianStream.h
@@ -25,6 +25,15 @@ namespace support {
namespace endian {
+template <typename value_type>
+inline void write_array(raw_ostream &os, ArrayRef<value_type> values,
+ endianness endian) {
+ for (const auto orig : values) {
+ value_type value = byte_swap<value_type>(orig, endian);
+ os.write((const char *)&value, sizeof(value_type));
+ }
+}
+
template <typename value_type>
inline void write(raw_ostream &os, value_type value, endianness endian) {
value = byte_swap<value_type>(value, endian);
diff --git a/llvm/lib/MC/DXContainerPSVInfo.cpp b/llvm/lib/MC/DXContainerPSVInfo.cpp
index 03df6be41a21c21..533659053c36f3d 100644
--- a/llvm/lib/MC/DXContainerPSVInfo.cpp
+++ b/llvm/lib/MC/DXContainerPSVInfo.cpp
@@ -147,4 +147,17 @@ void PSVRuntimeInfo::write(raw_ostream &OS, uint32_t Version) const {
OS.write(reinterpret_cast<const char *>(&SignatureElements[0]),
SignatureElements.size() * sizeof(v0::SignatureElement));
}
+
+ for (const auto &MaskVector : OutputVectorMasks)
+ support::endian::write_array(OS, ArrayRef<uint32_t>(MaskVector),
+ support::little);
+ support::endian::write_array(OS, ArrayRef<uint32_t>(PatchOrPrimMasks),
+ support::little);
+ for (const auto &MaskVector : InputOutputMap)
+ support::endian::write_array(OS, ArrayRef<uint32_t>(MaskVector),
+ support::little);
+ support::endian::write_array(OS, ArrayRef<uint32_t>(InputPatchMap),
+ support::little);
+ support::endian::write_array(OS, ArrayRef<uint32_t>(PatchOutputMap),
+ support::little);
}
diff --git a/llvm/lib/Object/DXContainer.cpp b/llvm/lib/Object/DXContainer.cpp
index df1f98213a9951f..16433f11eef625f 100644
--- a/llvm/lib/Object/DXContainer.cpp
+++ b/llvm/lib/Object/DXContainer.cpp
@@ -321,6 +321,68 @@ Error DirectX::PSVRuntimeInfo::parse(uint16_t ShaderKind) {
Current += PSize;
}
+ ArrayRef<uint8_t> OutputVectorCounts = getOutputVectorCounts();
+ uint8_t PatchConstOrPrimVectorCount = getPatchConstOrPrimVectorCount();
+ uint8_t InputVectorCount = getInputVectorCount();
+
+ auto maskDwordSize = [](uint8_t Vector) {
+ return (static_cast<uint32_t>(Vector) + 7) >> 3;
+ };
+
+ auto mapTableSize = [maskDwordSize](uint8_t X, uint8_t Y) {
+ return maskDwordSize(Y) * X * 4;
+ };
+
+ if (usesViewID()) {
+ for (uint32_t I = 0; I < 4; ++I) {
+ // The vector mask is one bit per component and 4 components per vector.
+ // We can compute the number of dwords required by rounding up to the next
+ // multiple of 8.
+ uint32_t NumDwords =
+ maskDwordSize(static_cast<uint32_t>(OutputVectorCounts[I]));
+ size_t NumBytes = NumDwords * sizeof(uint32_t);
+ OutputVectorMasks[I].Data = Data.substr(Current - Data.begin(), NumBytes);
+ Current += NumBytes;
+ }
+
+ if (ShaderStage == Triple::Hull && PatchConstOrPrimVectorCount > 0) {
+ uint32_t NumDwords = maskDwordSize(PatchConstOrPrimVectorCount);
+ size_t NumBytes = NumDwords * sizeof(uint32_t);
+ PatchOrPrimMasks.Data = Data.substr(Current - Data.begin(), NumBytes);
+ Current += NumBytes;
+ }
+ }
+
+ // Input/Output mapping table
+ for (uint32_t I = 0; I < 4; ++I) {
+ if (InputVectorCount == 0 || OutputVectorCounts[I] == 0)
+ continue;
+ uint32_t NumDwords = mapTableSize(InputVectorCount, OutputVectorCounts[I]);
+ size_t NumBytes = NumDwords * sizeof(uint32_t);
+ InputOutputMap[I].Data = Data.substr(Current - Data.begin(), NumBytes);
+ Current += NumBytes;
+ }
+
+ // Hull shader: Input/Patch mapping table
+ if (ShaderStage == Triple::Hull && PatchConstOrPrimVectorCount > 0 &&
+ InputVectorCount > 0) {
+ uint32_t NumDwords =
+ mapTableSize(InputVectorCount, PatchConstOrPrimVectorCount);
+ size_t NumBytes = NumDwords * sizeof(uint32_t);
+ InputPatchMap.Data = Data.substr(Current - Data.begin(), NumBytes);
+ Current += NumBytes;
+ }
+
+ // Domain Shader: Patch/Output mapping table
+ if (ShaderStage == Triple::Domain && PatchConstOrPrimVectorCount > 0 &&
+ OutputVectorCounts[0] > 0) {
+ uint32_t NumDwords =
+ mapTableSize(PatchConstOrPrimVectorCount, OutputVectorCounts[0]);
+ size_t NumBytes = NumDwords * sizeof(uint32_t);
+ PatchOutputMap.Data = Data.substr(Current - Data.begin(), NumBytes);
+ Current += NumBytes;
+ }
+
return Error::success();
}
diff --git a/llvm/lib/ObjectYAML/DXContainerEmitter.cpp b/llvm/lib/ObjectYAML/DXContainerEmitter.cpp
index c5d5d6551d401c5..de8b0f59844bfff 100644
--- a/llvm/lib/ObjectYAML/DXContainerEmitter.cpp
+++ b/llvm/lib/ObjectYAML/DXContainerEmitter.cpp
@@ -219,6 +219,25 @@ void DXContainerWriter::writeParts(raw_ostream &OS) {
El.Allocated, El.Kind, El.Type, El.Mode, El.DynamicMask,
El.Stream});
+ for (int I = 0; I < 4; ++I) {
+ PSV.OutputVectorMasks[I].insert(PSV.OutputVectorMasks[I].begin(),
+ P.Info->OutputVectorMasks[I].begin(),
+ P.Info->OutputVectorMasks[I].end());
+ PSV.InputOutputMap[I].insert(PSV.InputOutputMap[I].begin(),
+ P.Info->InputOutputMap[I].begin(),
+ P.Info->InputOutputMap[I].end());
+ }
+
+ PSV.PatchOrPrimMasks.insert(PSV.PatchOrPrimMasks.begin(),
+ P.Info->PatchOrPrimMasks.begin(),
+ P.Info->PatchOrPrimMasks.end());
+ PSV.InputPatchMap.insert(PSV.InputPatchMap.begin(),
+ P.Info->InputPatchMap.begin(),
+ P.Info->InputPatchMap.end());
+ PSV.PatchOutputMap.insert(PSV.PatchOutputMap.begin(),
+ P.Info->PatchOutputMap.begin(),
+ P.Info->PatchOutputMap.end());
+
PSV.finalize(static_cast<Triple::EnvironmentType>(
Triple::Pixel + P.Info->Info.ShaderStage));
PSV.write(OS, P.Info->Version);
diff --git a/llvm/lib/ObjectYAML/DXContainerYAML.cpp b/llvm/lib/ObjectYAML/DXContainerYAML.cpp
index 2b03098d7a5d08b..c7cf1ec9afc1f66 100644
--- a/llvm/lib/ObjectYAML/DXContainerYAML.cpp
+++ b/llvm/lib/ObjectYAML/DXContainerYAML.cpp
@@ -139,6 +139,24 @@ void MappingTraits<DXContainerYAML::PSVInfo>::mapping(
IO.mapRequired("SigInputElements", PSV.SigInputElements);
IO.mapRequired("SigOutputElements", PSV.SigOutputElements);
IO.mapRequired("SigPatchOrPrimElements", PSV.SigPatchOrPrimElements);
+
+ Triple::EnvironmentType Stage = dxbc::getShaderStage(PSV.Info.ShaderStage);
+ if (PSV.Info.UsesViewID) {
+ MutableArrayRef<SmallVector<llvm::yaml::Hex32>> MutableOutMasks(
+ PSV.OutputVectorMasks);
+ IO.mapRequired("OutputVectorMasks", MutableOutMasks);
+ if (Stage == Triple::EnvironmentType::Hull)
+ IO.mapRequired("PatchOrPrimMasks", PSV.PatchOrPrimMasks);
+ }
+ MutableArrayRef<SmallVector<llvm::yaml::Hex32>> MutableIOMap(
+ PSV.InputOutputMap);
+ IO.mapRequired("InputOutputMap", MutableIOMap);
+
+ if (Stage == Triple::EnvironmentType::Hull)
+ IO.mapRequired("InputPatchMap", PSV.InputPatchMap);
+
+ if (Stage == Triple::EnvironmentType::Domain)
+ IO.mapRequired("PatchOutputMap", PSV.PatchOutputMap);
}
void MappingTraits<DXContainerYAML::Part>::mapping(IO &IO,
diff --git a/llvm/test/ObjectYAML/DXContainer/DomainMaskVectors.yaml b/llvm/test/ObjectYAML/DXContainer/DomainMaskVectors.yaml
new file mode 100644
index 000000000000000..713fbc61e094b5a
--- /dev/null
+++ b/llvm/test/ObjectYAML/DXContainer/DomainMaskVectors.yaml
@@ -0,0 +1,200 @@
+# RUN: yaml2obj %s | obj2yaml | FileCheck %s
+--- !dxcontainer
+Header:
+ Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ]
+ Version:
+ Major: 1
+ Minor: 0
+ FileSize: 4616
+ PartCount: 8
+ PartOffsets: [ 64, 80, 140, 200, 580, 952, 2756, 2784 ]
+Parts:
+ - Name: SFI0
+ Size: 8
+ Flags:
+ Doubles: false
+ ComputeShadersPlusRawAndStructuredBuffers: false
+ UAVsAtEveryStage: false
+ Max64UAVs: false
+ MinimumPrecision: false
+ DX11_1_DoubleExtensions: false
+ DX11_1_ShaderExtensions: false
+ LEVEL9ComparisonFiltering: false
+ TiledResources: false
+ StencilRef: false
+ InnerCoverage: false
+ TypedUAVLoadAdditionalFormats: false
+ ROVs: false
+ ViewportAndRTArrayIndexFromAnyShaderFeedingRasterizer: false
+ WaveOps: false
+ Int64Ops: false
+ ViewID: true
+ Barycentrics: false
+ NativeLowPrecision: false
+ ShadingRate: false
+ Raytracing_Tier_1_1: false
+ SamplerFeedback: false
+ AtomicInt64OnTypedResource: false
+ AtomicInt64OnGroupShared: false
+ DerivativesInMeshAndAmpShaders: false
+ ResourceDescriptorHeapIndexing: false
+ SamplerDescriptorHeapIndexing: false
+ RESERVED: false
+ AtomicInt64OnHeapResource: false
+ AdvancedTextureOps: false
+ WriteableMSAATextures: false
+ NextUnusedBit: false
+ - Name: ISG1
+ Size: 52
+ - Name: OSG1
+ Size: 52
+ - Name: PSG1
+ Size: 372
+ - Name: PSV0
+ Size: 364
+ PSVInfo:
+ Version: 2
+ ShaderStage: 4
+ InputControlPointCount: 16
+ OutputPositionPresent: 1
+ TessellatorDomain: 3
+ MinimumWaveLaneCount: 0
+ MaximumWaveLaneCount: 4294967295
+ UsesViewID: 1
+ SigPatchConstOrPrimVectors: 7
+ SigInputVectors: 1
+ SigOutputVectors: [ 1, 0, 0, 0 ]
+ NumThreadsX: 0
+ NumThreadsY: 0
+ NumThreadsZ: 0
+ ResourceStride: 24
+ Resources:
+ - Type: 2
+ Space: 0
+ LowerBound: 0
+ UpperBound: 0
+ Kind: 13
+ Flags: 0
+ SigInputElements:
+ - Name: AAA_HSFoo
+ Indices: [ 0 ]
+ StartRow: 0
+ Cols: 3
+ StartCol: 0
+ Allocated: true
+ Kind: Arbitrary
+ ComponentType: Float32
+ Interpolation: Linear
+ DynamicMask: 0x0
+ Stream: 0
+ SigOutputElements:
+ - Name: ''
+ Indices: [ 0 ]
+ StartRow: 0
+ Cols: 4
+ StartCol: 0
+ Allocated: true
+ Kind: Position
+ ComponentType: Float32
+ Interpolation: LinearNoperspective
+ DynamicMask: 0x0
+ Stream: 0
+ SigPatchOrPrimElements:
+ - Name: ''
+ Indices: [ 0, 1, 2, 3 ]
+ StartRow: 0
+ Cols: 1
+ StartCol: 3
+ Allocated: true
+ Kind: TessFactor
+ ComponentType: Float32
+ Interpolation: Undefined
+ DynamicMask: 0x0
+ Stream: 0
+ - Name: ''
+ Indices: [ 0, 1 ]
+ StartRow: 4
+ Cols: 1
+ StartCol: 3
+ Allocated: true
+ Kind: InsideTessFactor
+ ComponentType: Float32
+ Interpolation: Undefined
+ DynamicMask: 0x0
+ Stream: 0
+ - Name: AAA
+ Indices: [ 0 ]
+ StartRow: 6
+ Cols: 4
+ StartCol: 0
+ Allocated: true
+ Kind: Arbitrary
+ ComponentType: Float32
+ Interpolation: Undefined
+ DynamicMask: 0x0
+ Stream: 0
+ - Name: BBB
+ Indices: [ 0, 1, 2 ]
+ StartRow: 0
+ Cols: 3
+ StartCol: 0
+ Allocated: true
+ Kind: Arbitrary
+ ComponentType: Float32
+ Interpolation: Undefined
+ DynamicMask: 0x0
+ Stream: 0
+ OutputVectorMasks:
+ - [ 0x1 ]
+ - [ ]
+ - [ ]
+ - [ ]
+ InputOutputMap:
+ - [ 0x0, 0xD, 0x0, 0x0 ]
+ - [ ]
+ - [ ]
+ - [ ]
+ PatchOutputMap: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 ]
+ - Name: STAT
+ Size: 1796
+ - Name: HASH
+ Size: 20
+ Hash:
+ IncludesSource: false
+ Digest: [ 0xD4, 0x48, 0xCB, 0xFE, 0xF9, 0xCD, 0x92, 0x7B,
+ 0xBD, 0x2B, 0x9A, 0x9D, 0xB4, 0x6F, 0x3E, 0x83 ]
+ - Name: DXIL
+ Size: 24
+ Program:
+ MajorVersion: 6
+ MinorVersion: 1
+ ShaderKind: 4
+ Size: 6
+ DXILMajorVersion: 1
+ DXILMinorVersion: 1
+ DXILSize: 0
+...
+
+# Verify the vector sizes and ViewID use.
+# CHECK: UsesViewID: 1
+# CHECK-NEXT: SigPatchConstOrPrimVectors: 7
+# CHECK-NEXT: SigInputVectors: 1
+# CHECK-NEXT: SigOutputVectors: [ 1, 0, 0, 0 ]
+
+# Verify the vector mask encodings.
+# CHECK: OutputVectorMasks:
+# CHECK-NEXT: - [ 0x1 ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ 0x0, 0xD, 0x0, 0x0 ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: PatchOutputMap: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
+# CHECK-NEXT: 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+# CHECK-NEXT: 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 ]
diff --git a/llvm/test/ObjectYAML/DXContainer/GeometryMaskVectors.yaml b/llvm/test/ObjectYAML/DXContainer/GeometryMaskVectors.yaml
new file mode 100644
index 000000000000000..bf29d0866b3628b
--- /dev/null
+++ b/llvm/test/ObjectYAML/DXContainer/GeometryMaskVectors.yaml
@@ -0,0 +1,174 @@
+# RUN: yaml2obj %s | obj2yaml | FileCheck %s
+--- !dxcontainer
+Header:
+ Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ]
+ Version:
+ Major: 1
+ Minor: 0
+ FileSize: 3836
+ PartCount: 7
+ PartOffsets: [ 60, 76, 204, 292, 584, 2092, 2120 ]
+Parts:
+ - Name: SFI0
+ Size: 8
+ Flags:
+ Doubles: false
+ ComputeShadersPlusRawAndStructuredBuffers: false
+ UAVsAtEveryStage: false
+ Max64UAVs: false
+ MinimumPrecision: false
+ DX11_1_DoubleExtensions: false
+ DX11_1_ShaderExtensions: false
+ LEVEL9ComparisonFiltering: false
+ TiledResources: false
+ StencilRef: false
+ InnerCoverage: false
+ TypedUAVLoadAdditionalFormats: false
+ ROVs: false
+ ViewportAndRTArrayIndexFromAnyShaderFeedingRasterizer: false
+ WaveOps: false
+ Int64Ops: false
+ ViewID: true
+ Barycentrics: false
+ NativeLowPrecision: false
+ ShadingRate: false
+ Raytracing_Tier_1_1: false
+ SamplerFeedback: false
+ AtomicInt64OnTypedResource: false
+ AtomicInt64OnGroupShared: false
+ DerivativesInMeshAndAmpShaders: false
+ ResourceDescriptorHeapIndexing: false
+ SamplerDescriptorHeapIndexing: false
+ RESERVED: false
+ AtomicInt64OnHeapResource: false
+ AdvancedTextureOps: false
+ WriteableMSAATextures: false
+ NextUnusedBit: false
+ - Name: ISG1
+ Size: 120
+ - Name: OSG1
+ Size: 80
+ - Name: PSV0
+ Size: 284
+ PSVInfo:
+ Version: 2
+ ShaderStage: 2
+ InputPrimitive: 3
+ OutputTopology: 1
+ OutputStreamMask: 3
+ OutputPositionPresent: 0
+ MinimumWaveLaneCount: 0
+ MaximumWaveLaneCount: 4294967295
+ UsesViewID: 1
+ MaxVertexCount: 3
+ SigInputVectors: 3
+ SigOutputVectors: [ 1, 1, 0, 0 ]
+ NumThreadsX: 0
+ NumThreadsY: 0
+ NumThreadsZ: 0
+ ResourceStride: 24
+ Resources: []
+ SigInputElements:
+ - Name: ''
+ Indices: [ 0 ]
+ StartRow: 0
+ Cols: 4
+ StartCol: 0
+ Allocated: true
+ Kind: Position
+ ComponentType: Float32
+ Interpolation: LinearNoperspective
+ DynamicMask: 0x0
+ Stream: 0
+ - Name: AAA
+ Indices: [ 2 ]
+ StartRow: 1
+ Cols: 2
+ StartCol: 0
+ Allocated: true
+ Kind: Arbitrary
+ ComponentType: Float32
+ Interpolation: Linear
+ DynamicMask: 0x0
+ Stream: 0
+ - Name: AAA
+ Indices: [ 3 ]
+ StartRow: 2
+ Cols: 4
+ StartCol: 0
+ Allocated: true
+ Kind: Arbitrary
+ ComponentType: Float32
+ Interpolation: Linear
+ DynamicMask: 0x0
+ Stream: 0
+ SigOutputElements:
+ - Name: BBB
+ Indices: [ 0 ]
+ StartRow: 0
+ Cols: 4
+ StartCol: 0
+ Allocated: true
+ Kind: Arbitrary
+ ComponentType: Float32
+ Interpolation: Linear
+ DynamicMask: 0x0
+ Stream: 0
+ - Name: CCC
+ Indices: [ 0 ]
+ StartRow: 0
+ Cols: 4
+ StartCol: 0
+ Allocated: true
+ Kind: Arbitrary
+ ComponentType: Float32
+ Interpolation: Linear
+ DynamicMask: 0x0
+ Stream: 1
+ SigPatchOrPrimElements: []
+ OutputVectorMasks:
+ - [ 0xE ]
+ - [ 0x5 ]
+ - [ ]
+ - [ ]
+ InputOutputMap:
+ - [ 0x2, 0x4, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ]
+ - [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x2, 0x4, 0x8 ]
+ - [ ]
+ - [ ]
+ - Name: STAT
+ Size: 1500
+ - Name: HASH
+ Size: 20
+ Hash:
+ IncludesSource: false
+ Digest: [ 0x10, 0xA2, 0x84, 0xA5, 0x76, 0xA6, 0x28, 0x82,
+ 0x21, 0x39, 0x1, 0xE0, 0x53, 0x19, 0xBE, 0x79 ]
+ - Name: DXIL
+ Size: 24
+ Program:
+ MajorVersion: 6
+ MinorVersion: 1
+ ShaderKind: 2
+ Size: 6
+ DXILMajorVersion: 1
+ DXILMinorVersion: 1
+ DXILSize: 0
+...
+
+# Verify the vector sizes.
+# CHECK: SigInputVectors: 3
+# CHECK-NEXT: SigOutputVectors: [ 1, 1, 0, 0 ]
+
+# Verify the vector mask encodings.
+# CHECK: OutputVectorMasks:
+# CHECK-NEXT: - [ 0xE ]
+# CHECK-NEXT: - [ 0x5 ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ 0x2, 0x4, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ]
+# CHECK-NEXT: - [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x2, 0x4, 0x8 ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
diff --git a/llvm/test/ObjectYAML/DXContainer/HullMaskVectors.yaml b/llvm/test/ObjectYAML/DXContainer/HullMaskVectors.yaml
new file mode 100644
index 000000000000000..0eaa2f8e97fb99c
--- /dev/null
+++ b/llvm/test/ObjectYAML/DXContainer/HullMaskVectors.yaml
@@ -0,0 +1,181 @@
+# RUN: yaml2obj %s | obj2yaml | FileCheck %s
+--- !dxcontainer
+Header:
+ Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ]
+ Version:
+ Major: 1
+ Minor: 0
+ FileSize: 4612
+ PartCount: 8
+ PartOffsets: [ 64, 80, 148, 208, 488, 740, 2468, 2496 ]
+Parts:
+ - Name: SFI0
+ Size: 8
+ Flags:
+ Doubles: false
+ ComputeShadersPlusRawAndStructuredBuffers: false
+ UAVsAtEveryStage: false
+ Max64UAVs: false
+ MinimumPrecision: false
+ DX11_1_DoubleExtensions: false
+ DX11_1_ShaderExtensions: false
+ LEVEL9ComparisonFiltering: false
+ TiledResources: false
+ StencilRef: false
+ InnerCoverage: false
+ TypedUAVLoadAdditionalFormats: false
+ ROVs: false
+ ViewportAndRTArrayIndexFromAnyShaderFeedingRasterizer: false
+ WaveOps: false
+ Int64Ops: false
+ ViewID: true
+ Barycentrics: false
+ NativeLowPrecision: false
+ ShadingRate: false
+ Raytracing_Tier_1_1: false
+ SamplerFeedback: false
+ AtomicInt64OnTypedResource: false
+ AtomicInt64OnGroupShared: false
+ DerivativesInMeshAndAmpShaders: false
+ ResourceDescriptorHeapIndexing: false
+ SamplerDescriptorHeapIndexing: false
+ RESERVED: false
+ AtomicInt64OnHeapResource: false
+ AdvancedTextureOps: false
+ WriteableMSAATextures: false
+ NextUnusedBit: false
+ - Name: ISG1
+ Size: 60
+ - Name: OSG1
+ Size: 52
+ - Name: PSG1
+ Size: 272
+ - Name: PSV0
+ Size: 244
+ PSVInfo:
+ Version: 2
+ ShaderStage: 3
+ InputControlPointCount: 32
+ OutputControlPointCount: 16
+ TessellatorDomain: 3
+ TessellatorOutputPrimitive: 3
+ MinimumWaveLaneCount: 0
+ MaximumWaveLaneCount: 4294967295
+ UsesViewID: 1
+ SigPatchConstOrPrimVectors: 7
+ SigInputVectors: 1
+ SigOutputVectors: [ 1, 0, 0, 0 ]
+ NumThreadsX: 0
+ NumThreadsY: 0
+ NumThreadsZ: 0
+ ResourceStride: 24
+ Resources: []
+ SigInputElements:
+ - Name: Sem_HSFoo_Input_qq
+ Indices: [ 0 ]
+ StartRow: 0
+ Cols: 4
+ StartCol: 0
+ Allocated: true
+ Kind: Arbitrary
+ ComponentType: Float32
+ Interpolation: Linear
+ DynamicMask: 0x0
+ Stream: 0
+ SigOutputElements:
+ - Name: Sem_HSFoo
+ Indices: [ 0 ]
+ StartRow: 0
+ Cols: 4
+ StartCol: 0
+ Allocated: true
+ Kind: Arbitrary
+ ComponentType: Float32
+ Interpolation: Linear
+ DynamicMask: 0x0
+ Stream: 0
+ SigPatchOrPrimElements:
+ - Name: ''
+ Indices: [ 0, 1, 2, 3 ]
+ StartRow: 0
+ Cols: 1
+ StartCol: 3
+ Allocated: true
+ Kind: TessFactor
+ ComponentType: Float32
+ Interpolation: Undefined
+ DynamicMask: 0x0
+ Stream: 0
+ - Name: ''
+ Indices: [ 0, 1 ]
+ StartRow: 4
+ Cols: 1
+ StartCol: 3
+ Allocated: true
+ Kind: InsideTessFactor
+ ComponentType: Float32
+ Interpolation: Undefined
+ DynamicMask: 0x0
+ Stream: 0
+ - Name: AAA
+ Indices: [ 0 ]
+ StartRow: 6
+ Cols: 4
+ StartCol: 0
+ Allocated: true
+ Kind: Arbitrary
+ ComponentType: Float32
+ Interpolation: Undefined
+ DynamicMask: 0x0
+ Stream: 0
+ OutputVectorMasks:
+ - [ 0x4 ]
+ - [ ]
+ - [ ]
+ - [ ]
+ PatchOrPrimMasks: [ 0x800080 ]
+ InputOutputMap:
+ - [ 0x5, 0x2, 0x4, 0xC ]
+ - [ ]
+ - [ ]
+ - [ ]
+ InputPatchMap: [ 0x880000, 0x8888, 0x800000, 0x880000 ]
+ - Name: STAT
+ Size: 1720
+ - Name: HASH
+ Size: 20
+ Hash:
+ IncludesSource: false
+ Digest: [ 0xF4, 0x87, 0x4C, 0x40, 0xFD, 0x7A, 0x89, 0xFE,
+ 0x1F, 0xC3, 0xAB, 0x8C, 0xC7, 0x18, 0xA9, 0xA ]
+ - Name: DXIL
+ Size: 24
+ Program:
+ MajorVersion: 6
+ MinorVersion: 1
+ ShaderKind: 3
+ Size: 5627
+ DXILMajorVersion: 1
+ DXILMinorVersion: 1
+ DXILSize: 0
+...
+
+# Verify the vector sizes and ViewID use.
+# CHECK: UsesViewID: 1
+# CHECK-NEXT: SigPatchConstOrPrimVectors: 7
+# CHECK-NEXT: SigInputVectors: 1
+# CHECK-NEXT: SigOutputVectors: [ 1, 0, 0, 0 ]
+
+# Verify the vector encodings.
+# CHECK: OutputVectorMasks:
+# CHECK-NEXT: - [ 0x4 ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: PatchOrPrimMasks: [ 0x800080 ]
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ 0x5, 0x2, 0x4, 0xC ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml
index 29e4b2468078595..982235549cddc6a 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml
@@ -17,8 +17,8 @@ Parts:
PayloadSizeInBytes: 4092
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
- SigInputVectors: 64
+ UsesViewID: 0
+ SigInputVectors: 0
SigOutputVectors: [ 8, 16, 32, 64 ]
ResourceStride: 16
Resources:
@@ -33,6 +33,11 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
- Name: DXIL
Size: 24
Program:
@@ -52,8 +57,8 @@ Parts:
# CHECK-NEXT: PayloadSizeInBytes: 4092
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID: 0
+# CHECK-NEXT: SigInputVectors: 0
# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
# CHECK-NEXT: ResourceStride: 16
# CHECK-NEXT: Resources:
@@ -68,4 +73,9 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml
index 8caae8cf868f007..629d45c65a20816 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml
@@ -16,8 +16,8 @@ Parts:
ShaderStage: 5
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
- SigInputVectors: 64
+ UsesViewID: 0
+ SigInputVectors: 0
SigOutputVectors: [ 8, 16, 32, 64 ]
ResourceStride: 16
Resources:
@@ -32,6 +32,11 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
- Name: DXIL
Size: 24
Program:
@@ -50,8 +55,8 @@ Parts:
# CHECK-NEXT: ShaderStage: 5
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID: 0
+# CHECK-NEXT: SigInputVectors: 0
# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
# CHECK-NEXT: ResourceStride: 16
# CHECK-NEXT: Resources:
@@ -66,4 +71,9 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml
index 8c7daa38a7ee809..941ec16544a2df4 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml
@@ -19,10 +19,10 @@ Parts:
TessellatorDomain: 2056
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
- SigPatchConstOrPrimVectors: 128
- SigInputVectors: 64
- SigOutputVectors: [ 8, 16, 32, 64 ]
+ UsesViewID: 0
+ SigPatchConstOrPrimVectors: 0
+ SigInputVectors: 0
+ SigOutputVectors: [ 0, 16, 32, 64 ]
ResourceStride: 16
Resources:
- Type: 1
@@ -36,6 +36,12 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
+ PatchOutputMap: []
- Name: DXIL
Size: 24
Program:
@@ -57,10 +63,10 @@ Parts:
# CHECK-NEXT: TessellatorDomain: 2056
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
-# CHECK-NEXT: SigPatchConstOrPrimVectors: 128
-# CHECK-NEXT: SigInputVectors: 64
-# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
+# CHECK-NEXT: UsesViewID: 0
+# CHECK-NEXT: SigPatchConstOrPrimVectors: 0
+# CHECK-NEXT: SigInputVectors: 0
+# CHECK-NEXT: SigOutputVectors: [ 0, 16, 32, 64 ]
# CHECK-NEXT: ResourceStride: 16
# CHECK-NEXT: Resources:
# CHECK-NEXT: - Type: 1
@@ -74,4 +80,10 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: PatchOutputMap: [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml
index 38f2a4cb79a648d..a666cc4464d4574 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml
@@ -20,9 +20,9 @@ Parts:
OutputPositionPresent: 1
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
+ UsesViewID: 0
MaxVertexCount: 4096
- SigInputVectors: 64
+ SigInputVectors: 0
SigOutputVectors: [ 8, 16, 32, 64 ]
ResourceStride: 16
Resources:
@@ -37,6 +37,11 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
- Name: DXIL
Size: 24
Program:
@@ -59,9 +64,9 @@ Parts:
# CHECK-NEXT: OutputPositionPresent: 1
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
+# CHECK-NEXT: UsesViewID: 0
# CHECK-NEXT: MaxVertexCount: 4096
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: SigInputVectors: 0
# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
# CHECK-NEXT: ResourceStride: 16
# CHECK-NEXT: Resources:
@@ -76,4 +81,9 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml
index 102907d3ed32583..c0f0f41e2318bd1 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml
@@ -20,10 +20,10 @@ Parts:
TessellatorOutputPrimitive: 8192
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
- SigPatchConstOrPrimVectors: 128
- SigInputVectors: 64
- SigOutputVectors: [ 8, 16, 32, 64 ]
+ UsesViewID: 0
+ SigPatchConstOrPrimVectors: 0
+ SigInputVectors: 0
+ SigOutputVectors: [ 0, 16, 32, 64 ]
ResourceStride: 16
Resources:
- Type: 1
@@ -37,6 +37,12 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
+ InputPatchMap: []
- Name: DXIL
Size: 24
Program:
@@ -59,10 +65,10 @@ Parts:
# CHECK-NEXT: TessellatorOutputPrimitive: 8192
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
-# CHECK-NEXT: SigPatchConstOrPrimVectors: 128
-# CHECK-NEXT: SigInputVectors: 64
-# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
+# CHECK-NEXT: UsesViewID: 0
+# CHECK-NEXT: SigPatchConstOrPrimVectors: 0
+# CHECK-NEXT: SigInputVectors: 0
+# CHECK-NEXT: SigOutputVectors: [ 0, 16, 32, 64 ]
# CHECK-NEXT: ResourceStride: 16
# CHECK-NEXT: Resources:
# CHECK-NEXT: - Type: 1
@@ -76,4 +82,10 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: InputPatchMap: [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml
index 2bf8a3d54f95128..f981cb99cb968d4 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml
@@ -21,10 +21,10 @@ Parts:
MaxOutputPrimitives: 4092
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
+ UsesViewID: 0
SigPrimVectors: 128
MeshOutputTopology: 16
- SigInputVectors: 64
+ SigInputVectors: 0
SigOutputVectors: [ 8, 16, 32, 64 ]
ResourceStride: 16
Resources:
@@ -39,6 +39,11 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
- Name: DXIL
Size: 24
Program:
@@ -62,10 +67,10 @@ Parts:
# CHECK-NEXT: MaxOutputPrimitives: 4092
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
+# CHECK-NEXT: UsesViewID: 0
# CHECK-NEXT: SigPrimVectors: 128
# CHECK-NEXT: MeshOutputTopology: 16
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: SigInputVectors: 0
# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
# CHECK-NEXT: ResourceStride: 16
# CHECK-NEXT: Resources:
@@ -80,4 +85,9 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml
index df4ef44937e97bf..a7b6804fe5fe6c6 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml
@@ -18,8 +18,8 @@ Parts:
SampleFrequency: 96
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
- SigInputVectors: 64
+ UsesViewID: 0
+ SigInputVectors: 0
SigOutputVectors: [ 8, 16, 32, 64 ]
ResourceStride: 16
Resources:
@@ -34,6 +34,11 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
- Name: DXIL
Size: 24
Program:
@@ -54,8 +59,8 @@ Parts:
# CHECK-NEXT: SampleFrequency: 96
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID: 0
+# CHECK-NEXT: SigInputVectors: 0
# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
# CHECK-NEXT: ResourceStride: 16
# CHECK-NEXT: Resources:
@@ -70,4 +75,9 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml
index 5bd8739cbf44209..a9590ba77040407 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml
@@ -17,8 +17,8 @@ Parts:
OutputPositionPresent: 1
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
- SigInputVectors: 64
+ UsesViewID: 0
+ SigInputVectors: 0
SigOutputVectors: [ 8, 16, 32, 64 ]
ResourceStride: 16
Resources:
@@ -33,6 +33,11 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
- Name: DXIL
Size: 24
Program:
@@ -52,8 +57,8 @@ Parts:
# CHECK-NEXT: OutputPositionPresent: 1
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID: 0
+# CHECK-NEXT: SigInputVectors: 0
# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
# CHECK-NEXT: ResourceStride: 16
# CHECK-NEXT: Resources:
@@ -68,4 +73,9 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml
index 48f5edf1d25f6e7..c1ad560f463e1e9 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml
@@ -17,8 +17,8 @@ Parts:
PayloadSizeInBytes: 4092
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
- SigInputVectors: 64
+ UsesViewID: 0
+ SigInputVectors: 0
SigOutputVectors: [ 8, 16, 32, 64 ]
NumThreadsX: 512
NumThreadsY: 1024
@@ -40,6 +40,11 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
- Name: DXIL
Size: 24
Program:
@@ -59,8 +64,8 @@ Parts:
# CHECK-NEXT: PayloadSizeInBytes: 4092
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID: 0
+# CHECK-NEXT: SigInputVectors: 0
# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
# CHECK-NEXT: NumThreadsX: 512
# CHECK-NEXT: NumThreadsY: 1024
@@ -82,4 +87,9 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml
index 16336f1db79c867..dc0ac3af9aa34b9 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml
@@ -16,8 +16,8 @@ Parts:
ShaderStage: 5
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
- SigInputVectors: 64
+ UsesViewID: 0
+ SigInputVectors: 0
SigOutputVectors: [ 8, 16, 32, 64 ]
NumThreadsX: 512
NumThreadsY: 1024
@@ -39,6 +39,11 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
- Name: DXIL
Size: 24
Program:
@@ -57,8 +62,8 @@ Parts:
# CHECK-NEXT: ShaderStage: 5
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID: 0
+# CHECK-NEXT: SigInputVectors: 0
# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
# CHECK-NEXT: NumThreadsX: 512
# CHECK-NEXT: NumThreadsY: 1024
@@ -80,4 +85,9 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml
index 4aab33ac342d81d..03e23b06d05e47d 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml
@@ -19,10 +19,10 @@ Parts:
TessellatorDomain: 2056
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
- SigPatchConstOrPrimVectors: 128
- SigInputVectors: 64
- SigOutputVectors: [ 8, 16, 32, 64 ]
+ UsesViewID: 0
+ SigPatchConstOrPrimVectors: 0
+ SigInputVectors: 0
+ SigOutputVectors: [ 0, 16, 32, 64 ]
NumThreadsX: 512
NumThreadsY: 1024
NumThreadsZ: 2048
@@ -43,6 +43,12 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
+ PatchOutputMap: []
- Name: DXIL
Size: 24
Program:
@@ -64,10 +70,10 @@ Parts:
# CHECK-NEXT: TessellatorDomain: 2056
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
-# CHECK-NEXT: SigPatchConstOrPrimVectors: 128
-# CHECK-NEXT: SigInputVectors: 64
-# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
+# CHECK-NEXT: UsesViewID: 0
+# CHECK-NEXT: SigPatchConstOrPrimVectors: 0
+# CHECK-NEXT: SigInputVectors: 0
+# CHECK-NEXT: SigOutputVectors: [ 0, 16, 32, 64 ]
# CHECK-NEXT: NumThreadsX: 512
# CHECK-NEXT: NumThreadsY: 1024
# CHECK-NEXT: NumThreadsZ: 2048
@@ -88,4 +94,10 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: PatchOutputMap: [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml
index 7fe7b84c1204c29..b4a5efd2276c527 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml
@@ -20,9 +20,9 @@ Parts:
OutputPositionPresent: 1
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
+ UsesViewID: 0
MaxVertexCount: 4096
- SigInputVectors: 64
+ SigInputVectors: 0
SigOutputVectors: [ 8, 16, 32, 64 ]
NumThreadsX: 512
NumThreadsY: 1024
@@ -44,6 +44,11 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
- Name: DXIL
Size: 24
Program:
@@ -66,9 +71,9 @@ Parts:
# CHECK-NEXT: OutputPositionPresent: 1
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
+# CHECK-NEXT: UsesViewID: 0
# CHECK-NEXT: MaxVertexCount: 4096
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: SigInputVectors: 0
# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
# CHECK-NEXT: NumThreadsX: 512
# CHECK-NEXT: NumThreadsY: 1024
@@ -90,4 +95,9 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml
index 4eb0dfcbd482bd9..a1c87343ee915b4 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml
@@ -20,10 +20,10 @@ Parts:
TessellatorOutputPrimitive: 8192
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
- SigPatchConstOrPrimVectors: 128
- SigInputVectors: 64
- SigOutputVectors: [ 8, 16, 32, 64 ]
+ UsesViewID: 0
+ SigPatchConstOrPrimVectors: 0
+ SigInputVectors: 0
+ SigOutputVectors: [ 0, 16, 32, 64 ]
NumThreadsX: 512
NumThreadsY: 1024
NumThreadsZ: 2048
@@ -44,6 +44,12 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
+ InputPatchMap: []
- Name: DXIL
Size: 24
Program:
@@ -66,10 +72,10 @@ Parts:
# CHECK-NEXT: TessellatorOutputPrimitive: 8192
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
-# CHECK-NEXT: SigPatchConstOrPrimVectors: 128
-# CHECK-NEXT: SigInputVectors: 64
-# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
+# CHECK-NEXT: UsesViewID: 0
+# CHECK-NEXT: SigPatchConstOrPrimVectors: 0
+# CHECK-NEXT: SigInputVectors: 0
+# CHECK-NEXT: SigOutputVectors: [ 0, 16, 32, 64 ]
# CHECK-NEXT: NumThreadsX: 512
# CHECK-NEXT: NumThreadsY: 1024
# CHECK-NEXT: NumThreadsZ: 2048
@@ -90,4 +96,10 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: InputPatchMap: [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml
index 873acba05a71ea7..6155a3e2354bce6 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml
@@ -21,10 +21,10 @@ Parts:
MaxOutputPrimitives: 4092
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
+ UsesViewID: 0
SigPrimVectors: 128
MeshOutputTopology: 16
- SigInputVectors: 64
+ SigInputVectors: 0
SigOutputVectors: [ 8, 16, 32, 64 ]
NumThreadsX: 512
NumThreadsY: 1024
@@ -46,6 +46,11 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
- Name: DXIL
Size: 24
Program:
@@ -69,10 +74,10 @@ Parts:
# CHECK-NEXT: MaxOutputPrimitives: 4092
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
+# CHECK-NEXT: UsesViewID: 0
# CHECK-NEXT: SigPrimVectors: 128
# CHECK-NEXT: MeshOutputTopology: 16
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: SigInputVectors: 0
# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
# CHECK-NEXT: NumThreadsX: 512
# CHECK-NEXT: NumThreadsY: 1024
@@ -94,4 +99,9 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml
index 63e2de6eefb0884..3fdd7be8fe7de90 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml
@@ -18,8 +18,8 @@ Parts:
SampleFrequency: 96
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
- SigInputVectors: 64
+ UsesViewID: 0
+ SigInputVectors: 0
SigOutputVectors: [ 8, 16, 32, 64 ]
NumThreadsX: 512
NumThreadsY: 1024
@@ -41,6 +41,11 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
- Name: DXIL
Size: 24
Program:
@@ -61,8 +66,8 @@ Parts:
# CHECK-NEXT: SampleFrequency: 96
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID: 0
+# CHECK-NEXT: SigInputVectors: 0
# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
# CHECK-NEXT: NumThreadsX: 512
# CHECK-NEXT: NumThreadsY: 1024
@@ -84,4 +89,9 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml
index fb595b51a0fdd4b..eb77fb1b10d77a2 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml
@@ -17,8 +17,8 @@ Parts:
OutputPositionPresent: 1
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
- SigInputVectors: 64
+ UsesViewID: 0
+ SigInputVectors: 0
SigOutputVectors: [ 8, 16, 32, 64 ]
NumThreadsX: 512
NumThreadsY: 1024
@@ -40,6 +40,11 @@ Parts:
SigInputElements: []
SigOutputElements: []
SigPatchOrPrimElements: []
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
- Name: DXIL
Size: 24
Program:
@@ -59,8 +64,8 @@ Parts:
# CHECK-NEXT: OutputPositionPresent: 1
# CHECK-NEXT: MinimumWaveLaneCount: 0
# CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID: 128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID: 0
+# CHECK-NEXT: SigInputVectors: 0
# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
# CHECK-NEXT: NumThreadsX: 512
# CHECK-NEXT: NumThreadsY: 1024
@@ -82,4 +87,9 @@ Parts:
# CHECK-NEXT: SigInputElements: []
# CHECK-NEXT: SigOutputElements: []
# CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
+# CHECK-NEXT: - [ ]
# CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/SigElements.yaml b/llvm/test/ObjectYAML/DXContainer/SigElements.yaml
index 8e2e5aa3e3e26bd..47a18a6487c975d 100644
--- a/llvm/test/ObjectYAML/DXContainer/SigElements.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/SigElements.yaml
@@ -18,8 +18,8 @@ Parts:
SampleFrequency: 96
MinimumWaveLaneCount: 0
MaximumWaveLaneCount: 4294967295
- UsesViewID: 128
- SigInputVectors: 64
+ UsesViewID: 0
+ SigInputVectors: 0
SigOutputVectors: [ 8, 16, 32, 64 ]
ResourceStride: 16
Resources:
@@ -78,6 +78,11 @@ Parts:
Interpolation: LinearSample
DynamicMask: 0x2
Stream: 3
+ InputOutputMap:
+ - [ ]
+ - [ ]
+ - [ ]
+ - [ ]
- Name: DXIL
Size: 24
Program:
diff --git a/llvm/tools/obj2yaml/dxcontainer2yaml.cpp b/llvm/tools/obj2yaml/dxcontainer2yaml.cpp
index 0b38839a720cbe1..e301ff94d82b593 100644
--- a/llvm/tools/obj2yaml/dxcontainer2yaml.cpp
+++ b/llvm/tools/obj2yaml/dxcontainer2yaml.cpp
@@ -108,6 +108,25 @@ dumpDXContainer(MemoryBufferRef Source) {
DXContainerYAML::SignatureElement(
El, PSVInfo->getStringTable(),
PSVInfo->getSemanticIndexTable()));
+
+ if (PSVInfo->usesViewID()) {
+ for (int I = 0; I < 4; ++I)
+ for (auto Mask : PSVInfo->getOutputVectorMasks(I))
+ NewPart.Info->OutputVectorMasks[I].push_back(Mask);
+ for (auto Mask : PSVInfo->getPatchOrPrimMasks())
+ NewPart.Info->PatchOrPrimMasks.push_back(Mask);
+ }
+
+ for (int I = 0; I < 4; ++I)
+ for (auto Mask : PSVInfo->getInputOutputMap(I))
+ NewPart.Info->InputOutputMap[I].push_back(Mask);
+
+ for (auto Mask : PSVInfo->getInputPatchMap())
+ NewPart.Info->InputPatchMap.push_back(Mask);
+
+ for (auto Mask : PSVInfo->getPatchOutputMap())
+ NewPart.Info->PatchOutputMap.push_back(Mask);
+
break;
}
case dxbc::PartType::Unknown:
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