[llvm] [BOLT] Improve handling of relocations targeting specific instructions (PR #66395)

[Vladislav Khmelevsky via llvm-commits]

yota9 wrote:

Thanks! Am I understand it right that this is from linker standpoint? In the final binary ld/addi would have just an imm operand.
But since we need lo12 offset between 1 instruction and the symbol we're addressing the 1st instruction (the second might have other HI address) and the linker knowing where we're addressing would find the 1st instruction, it's relocation and it's symbol to complete the lower part of the address.
If I'm right his schematic is soo weird to me. I mean at aarch64 we're doing:
adrp x0, symb  // PC-relative high 20 bit of address. I think it is ~ to auipc
// Any count of instructions
add x0, x0, symb // lo-12 part of address is offset in 4k page. Since we're addressing inside the 4k page this offset would never be changed.
So really only the adrp is PC-relative, the second one is page-relative offset. But RISC-V for some reason seems doesn't want to use such schematics and at linker time it "truly" calculates the lower part of the offset using the 1st instruction as a base and it's relocation to find the symbol. I really had to strain my brain to understood this schematic).

https://github.com/llvm/llvm-project/pull/66395