[llvm] [RISCV] Add testcase for isel load<(load (s128)), v8f16 (PR #66415)

[via llvm-commits]

https://github.com/hiraditya updated https://github.com/llvm/llvm-project/pull/66415:

>From b9526f20c5a70823d61a5553f51917fe8bf64c8c Mon Sep 17 00:00:00 2001
From: AdityaK <1894981+hiraditya at users.noreply.github.com>
Date: Thu, 14 Sep 2023 11:46:18 -0700
Subject: [PATCH] [RISCV] Add testcase for isel load<(load (s128)), v8f16

Relates to: #66245
---
 llvm/test/CodeGen/RISCV/rvv/pr66245.ll | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/pr66245.ll

diff --git a/llvm/test/CodeGen/RISCV/rvv/pr66245.ll b/llvm/test/CodeGen/RISCV/rvv/pr66245.ll
new file mode 100644
index 000000000000000..6eeadb296311a61
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/pr66245.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -target-abi=lp64d | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-linux"
+
+; CHECK: vsetivli
+
+define void @bar() local_unnamed_addr #0 {
+bb113:                                            ; preds = %bb112
+  %load = load <8 x half>, ptr poison, align 2
+  %fpext = fpext <8 x half> %load to <8 x float>
+  store <8 x float> %fpext, ptr poison, align 4
+  ret void
+}
+
+attributes #0 = { "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+v,+zba,+zbb,+zbs,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-h,-save-restore,-svinval,-svnapot,-svpbmt,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zbc,-zbkb,-zbkc,-zbkx,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
+