[llvm] [MachineBasicBlock] Fix use after free in SplitCriticalEdge (PR #66188)
Carl Ritson via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 14 00:56:41 PDT 2023
https://github.com/perlfu updated https://github.com/llvm/llvm-project/pull/66188:
>From c7b575fa97bf1e4f19ec8bb8279db3d1cc9f0d9c Mon Sep 17 00:00:00 2001
From: Carl Ritson <carl.ritson at amd.com>
Date: Wed, 13 Sep 2023 17:33:19 +0900
Subject: [PATCH 1/2] [MachineBasicBlock] Fix use after free in
SplitCriticalEdge
Remove use after free when attempting to update SlotIndexes
in MachineBasicBlock::SplitCriticalEdge.
Add support to targets for updating SlotIndexes when inserting or
removing branches.
---
llvm/include/llvm/CodeGen/MachineBasicBlock.h | 3 +-
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 13 ++--
llvm/lib/CodeGen/MachineBasicBlock.cpp | 69 ++++++-------------
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 52 ++++++++++----
llvm/lib/Target/AArch64/AArch64InstrInfo.h | 11 +--
llvm/lib/Target/AMDGPU/R600InstrInfo.cpp | 41 +++++++----
llvm/lib/Target/AMDGPU/R600InstrInfo.h | 8 +--
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 42 ++++++-----
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 8 +--
llvm/lib/Target/ARC/ARCInstrInfo.cpp | 22 ++++--
llvm/lib/Target/ARC/ARCInstrInfo.h | 8 +--
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 50 +++++++++-----
llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 8 +--
llvm/lib/Target/AVR/AVRInstrInfo.cpp | 16 ++++-
llvm/lib/Target/AVR/AVRInstrInfo.h | 8 +--
llvm/lib/Target/BPF/BPFInstrInfo.cpp | 15 ++--
llvm/lib/Target/BPF/BPFInstrInfo.h | 9 +--
llvm/lib/Target/CSKY/CSKYInstrInfo.cpp | 24 +++++--
llvm/lib/Target/CSKY/CSKYInstrInfo.h | 8 +--
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 57 ++++++++++-----
llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 8 +--
llvm/lib/Target/Lanai/LanaiInstrInfo.cpp | 25 +++++--
llvm/lib/Target/Lanai/LanaiInstrInfo.h | 10 +--
.../Target/LoongArch/LoongArchInstrInfo.cpp | 23 +++++--
.../lib/Target/LoongArch/LoongArchInstrInfo.h | 8 +--
llvm/lib/Target/M68k/M68kInstrInfo.cpp | 28 +++++---
llvm/lib/Target/M68k/M68kInstrInfo.h | 8 +--
llvm/lib/Target/MSP430/MSP430InstrInfo.cpp | 23 +++++--
llvm/lib/Target/MSP430/MSP430InstrInfo.h | 8 +--
llvm/lib/Target/Mips/MipsInstrInfo.cpp | 32 ++++++---
llvm/lib/Target/Mips/MipsInstrInfo.h | 11 +--
llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp | 29 +++++---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.h | 8 +--
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 62 ++++++++++-------
llvm/lib/Target/PowerPC/PPCInstrInfo.h | 8 +--
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 23 +++++--
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 8 +--
llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp | 13 ++--
llvm/lib/Target/SPIRV/SPIRVInstrInfo.h | 8 +--
llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 27 +++++---
llvm/lib/Target/Sparc/SparcInstrInfo.h | 8 +--
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 25 +++++--
llvm/lib/Target/SystemZ/SystemZInstrInfo.h | 8 +--
llvm/lib/Target/VE/VEInstrInfo.cpp | 44 +++++++-----
llvm/lib/Target/VE/VEInstrInfo.h | 8 +--
.../WebAssembly/WebAssemblyInstrInfo.cpp | 37 +++++++---
.../Target/WebAssembly/WebAssemblyInstrInfo.h | 8 +--
llvm/lib/Target/X86/X86InstrInfo.cpp | 44 +++++++-----
llvm/lib/Target/X86/X86InstrInfo.h | 8 +--
llvm/lib/Target/XCore/XCoreInstrInfo.cpp | 31 ++++++---
llvm/lib/Target/XCore/XCoreInstrInfo.h | 8 +--
51 files changed, 675 insertions(+), 396 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
index ed9fc8f7ec3d75e..74e7b98ca8a7526 100644
--- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
@@ -693,7 +693,8 @@ class MachineBasicBlock
/// layout was modified. If the block previously fell through to that block,
/// it may now need a branch. If it previously branched to another block, it
/// may now be able to fallthrough to the current layout successor.
- void updateTerminator(MachineBasicBlock *PreviousLayoutSuccessor);
+ void updateTerminator(MachineBasicBlock *PreviousLayoutSuccessor,
+ SlotIndexes *Indexes = nullptr);
// Machine-CFG mutators
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 1c2ca8678346472..8d40b8de8535f98 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -53,6 +53,7 @@ class ScheduleDAGMI;
class ScheduleHazardRecognizer;
class SDNode;
class SelectionDAG;
+class SlotIndexes;
class SMSchedule;
class SwingSchedulerDAG;
class RegScavenger;
@@ -682,7 +683,8 @@ class TargetInstrInfo : public MCInstrInfo {
/// If \p BytesRemoved is non-null, report the change in code size from the
/// removed instructions.
virtual unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const {
+ int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const {
llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
}
@@ -702,17 +704,18 @@ class TargetInstrInfo : public MCInstrInfo {
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const {
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const {
llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
}
unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
MachineBasicBlock *DestBB,
const DebugLoc &DL,
- int *BytesAdded = nullptr) const {
+ int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const {
return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
- BytesAdded);
+ BytesAdded, Indexes);
}
/// Object returned by analyzeLoopForPipelining. Allows software pipelining
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 280ced65db7d8c0..09df32afb37c00c 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -681,7 +681,7 @@ static int findJumpTableIndex(const MachineBasicBlock &MBB) {
}
void MachineBasicBlock::updateTerminator(
- MachineBasicBlock *PreviousLayoutSuccessor) {
+ MachineBasicBlock *PreviousLayoutSuccessor, SlotIndexes *Indexes) {
LLVM_DEBUG(dbgs() << "Updating terminators on " << printMBBReference(*this)
<< "\n");
@@ -693,7 +693,7 @@ void MachineBasicBlock::updateTerminator(
MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
SmallVector<MachineOperand, 4> Cond;
DebugLoc DL = findBranchDebugLoc();
- bool B = TII->analyzeBranch(*this, TBB, FBB, Cond);
+ bool B = TII->analyzeBranch(*this, TBB, FBB, Cond, /*AllowModify=*/false);
(void) B;
assert(!B && "UpdateTerminators requires analyzable predecessors!");
if (Cond.empty()) {
@@ -701,7 +701,7 @@ void MachineBasicBlock::updateTerminator(
// The block has an unconditional branch. If its successor is now its
// layout successor, delete the branch.
if (isLayoutSuccessor(TBB))
- TII->removeBranch(*this);
+ TII->removeBranch(*this, nullptr, Indexes);
} else {
// The block has an unconditional fallthrough, or the end of the block is
// unreachable.
@@ -717,7 +717,8 @@ void MachineBasicBlock::updateTerminator(
// If the unconditional successor block is not the current layout
// successor, insert a branch to jump to it.
if (!isLayoutSuccessor(PreviousLayoutSuccessor))
- TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL);
+ TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL,
+ nullptr, Indexes);
}
return;
}
@@ -729,11 +730,11 @@ void MachineBasicBlock::updateTerminator(
if (isLayoutSuccessor(TBB)) {
if (TII->reverseBranchCondition(Cond))
return;
- TII->removeBranch(*this);
- TII->insertBranch(*this, FBB, nullptr, Cond, DL);
+ TII->removeBranch(*this, nullptr, Indexes);
+ TII->insertBranch(*this, FBB, nullptr, Cond, DL, nullptr, Indexes);
} else if (isLayoutSuccessor(FBB)) {
- TII->removeBranch(*this);
- TII->insertBranch(*this, TBB, nullptr, Cond, DL);
+ TII->removeBranch(*this, nullptr, Indexes);
+ TII->insertBranch(*this, TBB, nullptr, Cond, DL, nullptr, Indexes);
}
return;
}
@@ -747,10 +748,10 @@ void MachineBasicBlock::updateTerminator(
// We had a fallthrough to the same basic block as the conditional jump
// targets. Remove the conditional jump, leaving an unconditional
// fallthrough or an unconditional jump.
- TII->removeBranch(*this);
+ TII->removeBranch(*this, nullptr, Indexes);
if (!isLayoutSuccessor(TBB)) {
Cond.clear();
- TII->insertBranch(*this, TBB, nullptr, Cond, DL);
+ TII->insertBranch(*this, TBB, nullptr, Cond, DL, nullptr, Indexes);
}
return;
}
@@ -760,14 +761,17 @@ void MachineBasicBlock::updateTerminator(
if (TII->reverseBranchCondition(Cond)) {
// We can't reverse the condition, add an unconditional branch.
Cond.clear();
- TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL);
+ TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL,
+ nullptr, Indexes);
return;
}
- TII->removeBranch(*this);
- TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL);
+ TII->removeBranch(*this, nullptr, Indexes);
+ TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL,
+ nullptr, Indexes);
} else if (!isLayoutSuccessor(PreviousLayoutSuccessor)) {
- TII->removeBranch(*this);
- TII->insertBranch(*this, TBB, PreviousLayoutSuccessor, Cond, DL);
+ TII->removeBranch(*this, nullptr, Indexes);
+ TII->insertBranch(*this, TBB, PreviousLayoutSuccessor, Cond, DL, nullptr,
+ Indexes);
}
}
@@ -1166,51 +1170,20 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
ReplaceUsesOfBlockWith(Succ, NMBB);
- // If updateTerminator() removes instructions, we need to remove them from
- // SlotIndexes.
- SmallVector<MachineInstr*, 4> Terminators;
- if (Indexes) {
- for (MachineInstr &MI :
- llvm::make_range(getFirstInstrTerminator(), instr_end()))
- Terminators.push_back(&MI);
- }
-
// Since we replaced all uses of Succ with NMBB, that should also be treated
// as the fallthrough successor
if (Succ == PrevFallthrough)
PrevFallthrough = NMBB;
if (!ChangedIndirectJump)
- updateTerminator(PrevFallthrough);
-
- if (Indexes) {
- SmallVector<MachineInstr*, 4> NewTerminators;
- for (MachineInstr &MI :
- llvm::make_range(getFirstInstrTerminator(), instr_end()))
- NewTerminators.push_back(&MI);
-
- for (MachineInstr *Terminator : Terminators) {
- if (!is_contained(NewTerminators, Terminator))
- Indexes->removeMachineInstrFromMaps(*Terminator);
- }
- }
+ updateTerminator(PrevFallthrough, Indexes);
// Insert unconditional "jump Succ" instruction in NMBB if necessary.
NMBB->addSuccessor(Succ);
if (!NMBB->isLayoutSuccessor(Succ)) {
SmallVector<MachineOperand, 4> Cond;
const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
- TII->insertBranch(*NMBB, Succ, nullptr, Cond, DL);
-
- if (Indexes) {
- for (MachineInstr &MI : NMBB->instrs()) {
- // Some instructions may have been moved to NMBB by updateTerminator(),
- // so we first remove any instruction that already has an index.
- if (Indexes->hasIndex(MI))
- Indexes->removeMachineInstrFromMaps(MI);
- Indexes->insertMachineInstrInMaps(MI);
- }
- }
+ TII->insertBranch(*NMBB, Succ, nullptr, Cond, DL, nullptr, Indexes);
}
// Fix PHI nodes in Succ so they refer to NMBB instead of this.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index a41ac0e44a7700b..012f56f306f0527 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -10,8 +10,8 @@
//
//===----------------------------------------------------------------------===//
-#include "AArch64ExpandImm.h"
#include "AArch64InstrInfo.h"
+#include "AArch64ExpandImm.h"
#include "AArch64FrameLowering.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64Subtarget.h"
@@ -31,6 +31,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
@@ -534,7 +535,8 @@ bool AArch64InstrInfo::reverseBranchCondition(
}
unsigned AArch64InstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+ int *BytesRemoved,
+ SlotIndexes *Indexes) const {
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
if (I == MBB.end())
return 0;
@@ -544,6 +546,8 @@ unsigned AArch64InstrInfo::removeBranch(MachineBasicBlock &MBB,
return 0;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
@@ -561,6 +565,8 @@ unsigned AArch64InstrInfo::removeBranch(MachineBasicBlock &MBB,
}
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
if (BytesRemoved)
*BytesRemoved = 8;
@@ -568,12 +574,18 @@ unsigned AArch64InstrInfo::removeBranch(MachineBasicBlock &MBB,
return 2;
}
-void AArch64InstrInfo::instantiateCondBranch(
- MachineBasicBlock &MBB, const DebugLoc &DL, MachineBasicBlock *TBB,
- ArrayRef<MachineOperand> Cond) const {
+void AArch64InstrInfo::instantiateCondBranch(MachineBasicBlock &MBB,
+ const DebugLoc &DL,
+ MachineBasicBlock *TBB,
+ ArrayRef<MachineOperand> Cond,
+ SlotIndexes *Indexes) const {
if (Cond[0].getImm() != -1) {
// Regular Bcc
- BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(AArch64::Bcc))
+ .addImm(Cond[0].getImm())
+ .addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
} else {
// Folded compare-and-branch
// Note that we use addOperand instead of addReg to keep the flags.
@@ -582,20 +594,27 @@ void AArch64InstrInfo::instantiateCondBranch(
if (Cond.size() > 3)
MIB.addImm(Cond[3].getImm());
MIB.addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MIB);
}
}
-unsigned AArch64InstrInfo::insertBranch(
- MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
- ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
+unsigned AArch64InstrInfo::insertBranch(MachineBasicBlock &MBB,
+ MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond,
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
if (!FBB) {
- if (Cond.empty()) // Unconditional branch?
- BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB);
- else
- instantiateCondBranch(MBB, DL, TBB, Cond);
+ if (Cond.empty()) { // Unconditional branch?
+ MachineInstr *MI = BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
+ } else
+ instantiateCondBranch(MBB, DL, TBB, Cond, Indexes);
if (BytesAdded)
*BytesAdded = 4;
@@ -604,8 +623,11 @@ unsigned AArch64InstrInfo::insertBranch(
}
// Two-way conditional branch.
- instantiateCondBranch(MBB, DL, TBB, Cond);
- BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB);
+ instantiateCondBranch(MBB, DL, TBB, Cond, Indexes);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB);
+
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
if (BytesAdded)
*BytesAdded = 8;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 24ff676218cbe90..cd6fcd32ee8ac11 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -225,12 +225,12 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
bool analyzeBranchPredicate(MachineBasicBlock &MBB,
MachineBranchPredicate &MBP,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
@@ -378,7 +378,8 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
MachineBasicBlock *TBB,
- ArrayRef<MachineOperand> Cond) const;
+ ArrayRef<MachineOperand> Cond,
+ SlotIndexes *Indexes) const;
bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
const MachineRegisterInfo &MRI) const;
bool removeCmpToZeroOrOne(MachineInstr &CmpInstr, unsigned SrcReg,
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
index 7f874b245b8f4f4..7d495553e945a7a 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -19,6 +19,7 @@
#include "R600Subtarget.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
using namespace llvm;
@@ -730,14 +731,16 @@ unsigned R600InstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert(!BytesAdded && "code size not handled");
if (!FBB) {
if (Cond.empty()) {
- BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(TBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 1;
} else {
MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
@@ -745,9 +748,11 @@ unsigned R600InstrInfo::insertBranch(MachineBasicBlock &MBB,
addFlag(*PredSet, 0, MO_FLAG_PUSH);
PredSet->getOperand(2).setImm(Cond[1].getImm());
- BuildMI(&MBB, DL, get(R600::JUMP_COND))
- .addMBB(TBB)
- .addReg(R600::PREDICATE_BIT, RegState::Kill);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(R600::JUMP_COND))
+ .addMBB(TBB)
+ .addReg(R600::PREDICATE_BIT, RegState::Kill);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
if (CfAlu == MBB.end())
return 1;
@@ -760,10 +765,14 @@ unsigned R600InstrInfo::insertBranch(MachineBasicBlock &MBB,
assert(PredSet && "No previous predicate !");
addFlag(*PredSet, 0, MO_FLAG_PUSH);
PredSet->getOperand(2).setImm(Cond[1].getImm());
- BuildMI(&MBB, DL, get(R600::JUMP_COND))
- .addMBB(TBB)
- .addReg(R600::PREDICATE_BIT, RegState::Kill);
- BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(FBB);
+ MachineInstr *CondBr = BuildMI(&MBB, DL, get(R600::JUMP_COND))
+ .addMBB(TBB)
+ .addReg(R600::PREDICATE_BIT, RegState::Kill);
+ MachineInstr *UncondBr = BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(FBB);
+ if (Indexes) {
+ Indexes->insertMachineInstrInMaps(*CondBr);
+ Indexes->insertMachineInstrInMaps(*UncondBr);
+ }
MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
if (CfAlu == MBB.end())
return 2;
@@ -773,8 +782,8 @@ unsigned R600InstrInfo::insertBranch(MachineBasicBlock &MBB,
}
}
-unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "code size not handled");
// Note : we leave PRED* instructions there.
@@ -792,6 +801,8 @@ unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB,
case R600::JUMP_COND: {
MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
clearFlag(*predSet, 0, MO_FLAG_PUSH);
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
if (CfAlu == MBB.end())
@@ -801,6 +812,8 @@ unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB,
break;
}
case R600::JUMP:
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
break;
}
@@ -817,6 +830,8 @@ unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB,
case R600::JUMP_COND: {
MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
clearFlag(*predSet, 0, MO_FLAG_PUSH);
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
if (CfAlu == MBB.end())
@@ -826,6 +841,8 @@ unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB,
break;
}
case R600::JUMP:
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
break;
}
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.h b/llvm/lib/Target/AMDGPU/R600InstrInfo.h
index f720e4656348c83..5557b435f1d0c51 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.h
@@ -170,11 +170,11 @@ class R600InstrInfo final : public R600GenInstrInfo {
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
bool isPredicated(const MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 38b5e0114903cdf..72ee0a3a6725ee3 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2843,14 +2843,16 @@ bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
return analyzeBranchImpl(MBB, I, TBB, FBB, Cond, AllowModify);
}
-unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
unsigned Count = 0;
unsigned RemovedSize = 0;
for (MachineInstr &MI : llvm::make_early_inc_range(MBB.terminators())) {
// Skip over artificial terminators when removing instructions.
if (MI.isBranch() || MI.isReturn()) {
RemovedSize += getInstSizeInBytes(MI);
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(MI);
MI.eraseFromParent();
++Count;
}
@@ -2873,21 +2875,26 @@ unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
if (!FBB && Cond.empty()) {
- BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
- .addMBB(TBB);
+ MachineInstr *UncondBr =
+ BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH)).addMBB(TBB);
if (BytesAdded)
*BytesAdded = ST.hasOffset3fBug() ? 8 : 4;
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*UncondBr);
return 1;
}
- if(Cond.size() == 1 && Cond[0].isReg()) {
- BuildMI(&MBB, DL, get(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO))
- .add(Cond[0])
- .addMBB(TBB);
- return 1;
+ if (Cond.size() == 1 && Cond[0].isReg()) {
+ MachineInstr *UncondBr =
+ BuildMI(&MBB, DL, get(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO))
+ .add(Cond[0])
+ .addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*UncondBr);
+ return 1;
}
assert(TBB && Cond[0].isImm());
@@ -2899,6 +2906,8 @@ unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineInstr *CondBr =
BuildMI(&MBB, DL, get(Opcode))
.addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*CondBr);
// Copy the flags onto the implicit condition register operand.
preserveCondRegFlags(CondBr->getOperand(1), Cond[1]);
@@ -2911,12 +2920,9 @@ unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB,
assert(TBB && FBB);
- MachineInstr *CondBr =
- BuildMI(&MBB, DL, get(Opcode))
- .addMBB(TBB);
+ MachineInstr *CondBr = BuildMI(&MBB, DL, get(Opcode)).addMBB(TBB);
fixImplicitOperands(*CondBr);
- BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
- .addMBB(FBB);
+ MachineInstr *UncondBr = BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH)).addMBB(FBB);
MachineOperand &CondReg = CondBr->getOperand(1);
CondReg.setIsUndef(Cond[1].isUndef());
@@ -2924,6 +2930,10 @@ unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB,
if (BytesAdded)
*BytesAdded = ST.hasOffset3fBug() ? 16 : 8;
+ if (Indexes) {
+ Indexes->insertMachineInstrInMaps(*CondBr);
+ Indexes->insertMachineInstrInMaps(*UncondBr);
+ }
return 2;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index e85917a4c0f3296..25568845361e584 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -331,13 +331,13 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
bool reverseBranchCondition(
SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
index fe78a98837cf970..74d36c72f9ee179 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
@@ -18,6 +18,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Debug.h"
@@ -251,8 +252,8 @@ bool ARCInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
return false;
}
-unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "Code size not handled");
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
if (I == MBB.end())
@@ -263,6 +264,8 @@ unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,
return 0;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
@@ -274,6 +277,8 @@ unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,
return 1;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
return 2;
}
@@ -370,7 +375,8 @@ unsigned ARCInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
assert(!BytesAdded && "Code size not handled.");
// Shouldn't be a fall through.
@@ -379,7 +385,9 @@ unsigned ARCInstrInfo::insertBranch(MachineBasicBlock &MBB,
"ARC branch conditions have two components!");
if (Cond.empty()) {
- BuildMI(&MBB, DL, get(ARC::BR)).addMBB(TBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(ARC::BR)).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 1;
}
int BccOpc = Cond[1].isImm() ? ARC::BRcc_ru6_p : ARC::BRcc_rr_p;
@@ -388,6 +396,8 @@ unsigned ARCInstrInfo::insertBranch(MachineBasicBlock &MBB,
for (unsigned i = 0; i < 3; i++) {
MIB.add(Cond[i]);
}
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MIB);
// One-way conditional branch.
if (!FBB) {
@@ -395,7 +405,9 @@ unsigned ARCInstrInfo::insertBranch(MachineBasicBlock &MBB,
}
// Two-way conditional branch.
- BuildMI(&MBB, DL, get(ARC::BR)).addMBB(FBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(ARC::BR)).addMBB(FBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 2;
}
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.h b/llvm/lib/Target/ARC/ARCInstrInfo.h
index c55c9535ec296b8..be618e953a9ce36 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.h
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.h
@@ -57,11 +57,11 @@ class ARCInstrInfo : public ARCGenInstrInfo {
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &, MCRegister DestReg, MCRegister SrcReg,
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 1ffdde0360cf623..d9efa39aeadd42f 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -469,7 +469,8 @@ bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
}
unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+ int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
@@ -481,6 +482,8 @@ unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB,
return 0;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
@@ -491,6 +494,8 @@ unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB,
return 1;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
return 2;
}
@@ -499,8 +504,8 @@ unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
assert(!BytesAdded && "code size not handled");
ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
int BOpc = !AFI->isThumbFunction()
@@ -517,33 +522,44 @@ unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB,
// For conditional branches, we use addOperand to preserve CPSR flags.
if (!FBB) {
+ MachineInstr *MI;
if (Cond.empty()) { // Unconditional branch?
if (isThumb)
- BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).add(predOps(ARMCC::AL));
+ MI = BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).add(predOps(ARMCC::AL));
else
- BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
+ MI = BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
} else if (Cond.size() == 2) {
- BuildMI(&MBB, DL, get(BccOpc))
- .addMBB(TBB)
- .addImm(Cond[0].getImm())
- .add(Cond[1]);
+ MI = BuildMI(&MBB, DL, get(BccOpc))
+ .addMBB(TBB)
+ .addImm(Cond[0].getImm())
+ .add(Cond[1]);
} else
- BuildMI(&MBB, DL, get(Cond[0].getImm())).add(Cond[1]).addMBB(TBB);
+ MI = BuildMI(&MBB, DL, get(Cond[0].getImm())).add(Cond[1]).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 1;
}
// Two-way conditional branch.
+ MachineInstr *CondBr, *UncondBr;
if (Cond.size() == 2)
- BuildMI(&MBB, DL, get(BccOpc))
- .addMBB(TBB)
- .addImm(Cond[0].getImm())
- .add(Cond[1]);
+ CondBr = BuildMI(&MBB, DL, get(BccOpc))
+ .addMBB(TBB)
+ .addImm(Cond[0].getImm())
+ .add(Cond[1]);
else if (Cond.size() == 3)
- BuildMI(&MBB, DL, get(Cond[0].getImm())).add(Cond[1]).addMBB(TBB);
+ CondBr = BuildMI(&MBB, DL, get(Cond[0].getImm())).add(Cond[1]).addMBB(TBB);
+
if (isThumb)
- BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL));
+ UncondBr = BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL));
else
- BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
+ UncondBr = BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
+
+ if (Indexes) {
+ Indexes->insertMachineInstrInMaps(*CondBr);
+ Indexes->insertMachineInstrInMaps(*UncondBr);
+ }
+
return 2;
}
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 5efcc1a0d9fc073..c7c3554d9d1bbd0 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -143,12 +143,12 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
index b9d27c78ce8e41e..b9d0ab552a19d90 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
@@ -17,6 +17,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCContext.h"
@@ -399,7 +400,8 @@ unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
if (BytesAdded)
*BytesAdded = 0;
@@ -413,6 +415,8 @@ unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB,
auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(TBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(MI);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(MI);
return 1;
}
@@ -423,6 +427,8 @@ unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB,
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(CondMI);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(CondMI);
++Count;
if (FBB) {
@@ -430,14 +436,16 @@ unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB,
auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(FBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(MI);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(MI);
++Count;
}
return Count;
}
-unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
if (BytesRemoved)
*BytesRemoved = 0;
@@ -459,6 +467,8 @@ unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB,
// Remove the branch.
if (BytesRemoved)
*BytesRemoved += getInstSizeInBytes(*I);
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
++Count;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.h b/llvm/lib/Target/AVR/AVRInstrInfo.h
index 290177f5eec6665..28bd92bb6b5dbd6 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.h
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.h
@@ -99,10 +99,10 @@ class AVRInstrInfo : public AVRGenInstrInfo {
bool AllowModify = false) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInstrInfo.cpp
index 2209f1f1462b43f..afb513a6c8e2e35 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.cpp
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.cpp
@@ -15,6 +15,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Support/ErrorHandling.h"
#include <cassert>
@@ -221,8 +222,8 @@ unsigned BPFInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
assert(!BytesAdded && "code size not handled");
// Shouldn't be a fall through.
@@ -231,15 +232,17 @@ unsigned BPFInstrInfo::insertBranch(MachineBasicBlock &MBB,
if (Cond.empty()) {
// Unconditional branch
assert(!FBB && "Unconditional branch with multiple successors!");
- BuildMI(&MBB, DL, get(BPF::JMP)).addMBB(TBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(BPF::JMP)).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 1;
}
llvm_unreachable("Unexpected conditional branch");
}
-unsigned BPFInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned BPFInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.end();
@@ -252,6 +255,8 @@ unsigned BPFInstrInfo::removeBranch(MachineBasicBlock &MBB,
if (I->getOpcode() != BPF::JMP)
break;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
++Count;
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.h b/llvm/lib/Target/BPF/BPFInstrInfo.h
index 354aca1bd2f93b4..1594babeb2ebfe0 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.h
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.h
@@ -52,12 +52,13 @@ class BPFInstrInfo : public BPFGenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
+
private:
void expandMEMCPY(MachineBasicBlock::iterator) const;
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
index e5581bcdc397580..cd1a148e7c010fe 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
@@ -15,6 +15,7 @@
#include "CSKYMachineFunctionInfo.h"
#include "CSKYTargetMachine.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/MC/MCContext.h"
#define DEBUG_TYPE "csky-instr-info"
@@ -110,8 +111,8 @@ bool CSKYInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
return true;
}
-unsigned CSKYInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned CSKYInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
if (BytesRemoved)
*BytesRemoved = 0;
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
@@ -125,6 +126,8 @@ unsigned CSKYInstrInfo::removeBranch(MachineBasicBlock &MBB,
// Remove the branch.
if (BytesRemoved)
*BytesRemoved += getInstSizeInBytes(*I);
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
@@ -138,6 +141,8 @@ unsigned CSKYInstrInfo::removeBranch(MachineBasicBlock &MBB,
// Remove the branch.
if (BytesRemoved)
*BytesRemoved += getInstSizeInBytes(*I);
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
return 2;
}
@@ -151,9 +156,12 @@ CSKYInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
return MI.getOperand(NumOp - 1).getMBB();
}
-unsigned CSKYInstrInfo::insertBranch(
- MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
- ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
+unsigned CSKYInstrInfo::insertBranch(MachineBasicBlock &MBB,
+ MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond,
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
if (BytesAdded)
*BytesAdded = 0;
@@ -167,6 +175,8 @@ unsigned CSKYInstrInfo::insertBranch(
MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(TBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(MI);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(MI);
return 1;
}
@@ -175,6 +185,8 @@ unsigned CSKYInstrInfo::insertBranch(
MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).addMBB(TBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(CondMI);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(CondMI);
// One-way conditional branch.
if (!FBB)
@@ -184,6 +196,8 @@ unsigned CSKYInstrInfo::insertBranch(
MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(FBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(MI);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(MI);
return 2;
}
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.h b/llvm/lib/Target/CSKY/CSKYInstrInfo.h
index dbb69a7a8798080..43e7f7a3fbb00c9 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.h
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.h
@@ -59,16 +59,16 @@ class CSKYInstrInfo : public CSKYGenInstrInfo {
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 6f0210763bc5f35..ccee614e783a828 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -36,6 +36,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -603,7 +604,8 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
}
unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+ int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "code size not handled");
LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
@@ -618,7 +620,9 @@ unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
return Count;
if (Count && (I->getOpcode() == Hexagon::J2_jump))
llvm_unreachable("Malformed basic block: unconditional branch not last");
- MBB.erase(&MBB.back());
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
+ I->eraseFromParent();
I = MBB.end();
++Count;
}
@@ -629,8 +633,8 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
unsigned BOpc = Hexagon::J2_jump;
unsigned BccOpc = Hexagon::J2_jumpt;
assert(validateBranchCond(Cond) && "Invalid branching condition");
@@ -656,10 +660,12 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
!analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
reverseBranchCondition(Cond);
- removeBranch(MBB);
- return insertBranch(MBB, TBB, nullptr, Cond, DL);
+ removeBranch(MBB, nullptr, Indexes);
+ return insertBranch(MBB, TBB, nullptr, Cond, DL, nullptr, Indexes);
}
- BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
} else if (isEndLoopN(Cond[0].getImm())) {
int EndLoopOp = Cond[0].getImm();
assert(Cond[1].isMBB());
@@ -671,7 +677,9 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
Loop->getOperand(0).setMBB(TBB);
// Add the ENDLOOP after the finding the LOOP0.
- BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
} else if (isNewValueJump(Cond[0].getImm())) {
assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
// New value jump
@@ -680,20 +688,30 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
<< printMBBReference(MBB););
+ MachineInstr *MI = nullptr;
if (Cond[2].isReg()) {
unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
- BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
- addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
+ MI = BuildMI(&MBB, DL, get(BccOpc))
+ .addReg(Cond[1].getReg(), Flags1)
+ .addReg(Cond[2].getReg(), Flags2)
+ .addMBB(TBB);
} else if(Cond[2].isImm()) {
- BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
- addImm(Cond[2].getImm()).addMBB(TBB);
+ MI = BuildMI(&MBB, DL, get(BccOpc))
+ .addReg(Cond[1].getReg(), Flags1)
+ .addImm(Cond[2].getImm())
+ .addMBB(TBB);
} else
llvm_unreachable("Invalid condition for branching");
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
} else {
assert((Cond.size() == 2) && "Malformed cond vector");
const MachineOperand &RO = Cond[1];
unsigned Flags = getUndefRegState(RO.isUndef());
- BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
+ MachineInstr *MI =
+ BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
}
return 1;
}
@@ -713,13 +731,20 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
Loop->getOperand(0).setMBB(TBB);
// Add the ENDLOOP after the finding the LOOP0.
- BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
} else {
const MachineOperand &RO = Cond[1];
unsigned Flags = getUndefRegState(RO.isUndef());
- BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
+ MachineInstr *MI =
+ BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
}
- BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 2;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index 0bc0877f6e70670..f444ec873ebf5bf 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -111,8 +111,8 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
/// Remove the branching code at the end of the specific MBB.
/// This is only invoked in cases where analyzeBranch returns success. It
/// returns the number of instructions that were removed.
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
/// Insert branch code into the end of the specified MachineBasicBlock.
/// The operands to this method are the same as those
@@ -126,8 +126,8 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
/// merging needs to be disabled.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
/// Analyze loop L, which must be a single-basic-block loop, and if the
/// conditions can be understood enough produce a PipelinerLoopInfo object.
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
index aa7e8846406dd85..ec079453735be01 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
@@ -19,6 +19,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
@@ -657,8 +658,8 @@ unsigned LanaiInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TrueBlock,
MachineBasicBlock *FalseBlock,
ArrayRef<MachineOperand> Condition,
- const DebugLoc &DL,
- int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
// Shouldn't be a fall through.
assert(TrueBlock && "insertBranch must not be told to insert a fallthrough");
assert(!BytesAdded && "code size not handled");
@@ -666,7 +667,9 @@ unsigned LanaiInstrInfo::insertBranch(MachineBasicBlock &MBB,
// If condition is empty then an unconditional branch is being inserted.
if (Condition.empty()) {
assert(!FalseBlock && "Unconditional branch with multiple successors!");
- BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(TrueBlock);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(TrueBlock);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 1;
}
@@ -674,19 +677,25 @@ unsigned LanaiInstrInfo::insertBranch(MachineBasicBlock &MBB,
assert((Condition.size() == 1) &&
"Lanai branch conditions should have one component.");
unsigned ConditionalCode = Condition[0].getImm();
- BuildMI(&MBB, DL, get(Lanai::BRCC)).addMBB(TrueBlock).addImm(ConditionalCode);
+ MachineInstr *CondBr = BuildMI(&MBB, DL, get(Lanai::BRCC))
+ .addMBB(TrueBlock)
+ .addImm(ConditionalCode);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*CondBr);
// If no false block, then false behavior is fall through and no branch needs
// to be inserted.
if (!FalseBlock)
return 1;
- BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(FalseBlock);
+ MachineInstr *UncondBr = BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(FalseBlock);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*UncondBr);
return 2;
}
-unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator Instruction = MBB.end();
@@ -702,6 +711,8 @@ unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB,
}
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*Instruction);
Instruction->eraseFromParent();
Instruction = MBB.end();
++Count;
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.h b/llvm/lib/Target/Lanai/LanaiInstrInfo.h
index 62f6240c6e4681f..a90f47eb37595f6 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.h
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.h
@@ -89,8 +89,8 @@ class LanaiInstrInfo : public LanaiGenInstrInfo {
SmallVectorImpl<MachineOperand> &Condition,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
// For a comparison instruction, return the source registers in SrcReg and
// SrcReg2 if having two register operands, and the value it compares against
@@ -138,9 +138,9 @@ class LanaiInstrInfo : public LanaiGenInstrInfo {
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock,
MachineBasicBlock *FalseBlock,
- ArrayRef<MachineOperand> Condition,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ ArrayRef<MachineOperand> Condition, const DebugLoc &DL,
+ int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
};
static inline bool isSPLSOpcode(unsigned Opcode) {
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
index 9fad3377a8fd842..79eea5d328897ce 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
@@ -17,6 +17,7 @@
#include "MCTargetDesc/LoongArchMCTargetDesc.h"
#include "MCTargetDesc/LoongArchMatInt.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/MC/MCInstBuilder.h"
using namespace llvm;
@@ -319,7 +320,8 @@ bool LoongArchInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
}
unsigned LoongArchInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+ int *BytesRemoved,
+ SlotIndexes *Indexes) const {
if (BytesRemoved)
*BytesRemoved = 0;
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
@@ -332,6 +334,8 @@ unsigned LoongArchInstrInfo::removeBranch(MachineBasicBlock &MBB,
// Remove the branch.
if (BytesRemoved)
*BytesRemoved += getInstSizeInBytes(*I);
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
@@ -345,15 +349,20 @@ unsigned LoongArchInstrInfo::removeBranch(MachineBasicBlock &MBB,
// Remove the branch.
if (BytesRemoved)
*BytesRemoved += getInstSizeInBytes(*I);
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
return 2;
}
// Inserts a branch into the end of the specific MachineBasicBlock, returning
// the number of instructions inserted.
-unsigned LoongArchInstrInfo::insertBranch(
- MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
- ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
+unsigned LoongArchInstrInfo::insertBranch(MachineBasicBlock &MBB,
+ MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond,
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
if (BytesAdded)
*BytesAdded = 0;
@@ -367,6 +376,8 @@ unsigned LoongArchInstrInfo::insertBranch(
MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(TBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(MI);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(MI);
return 1;
}
@@ -377,6 +388,8 @@ unsigned LoongArchInstrInfo::insertBranch(
MIB.addMBB(TBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(*MIB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MIB);
// One-way conditional branch.
if (!FBB)
@@ -386,6 +399,8 @@ unsigned LoongArchInstrInfo::insertBranch(
MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(FBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(MI);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(MI);
return 2;
}
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
index cf83abf27a1e337..539ef9c8387448f 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
@@ -62,13 +62,13 @@ class LoongArchInstrInfo : public LoongArchGenInstrInfo {
bool isBranchOffsetInRange(unsigned BranchOpc,
int64_t BrOffset) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &dl,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &dl, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
void insertIndirectBranch(MachineBasicBlock &MBB,
MachineBasicBlock &NewDestBB,
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
index 8d36e94d8e6960a..4fd3ff84a30a45f 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -24,6 +24,7 @@
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Regex.h"
@@ -254,8 +255,8 @@ bool M68kInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, AllowModify);
}
-unsigned M68kInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned M68kInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.end();
@@ -269,6 +270,8 @@ unsigned M68kInstrInfo::removeBranch(MachineBasicBlock &MBB,
getCondFromBranchOpc(I->getOpcode()) == M68k::COND_INVALID)
break;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
++Count;
@@ -277,9 +280,12 @@ unsigned M68kInstrInfo::removeBranch(MachineBasicBlock &MBB,
return Count;
}
-unsigned M68kInstrInfo::insertBranch(
- MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
- ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
+unsigned M68kInstrInfo::insertBranch(MachineBasicBlock &MBB,
+ MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond,
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
// Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) &&
@@ -289,7 +295,9 @@ unsigned M68kInstrInfo::insertBranch(
if (Cond.empty()) {
// Unconditional branch?
assert(!FBB && "Unconditional branch with multiple successors!");
- BuildMI(&MBB, DL, get(M68k::BRA8)).addMBB(TBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(M68k::BRA8)).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 1;
}
@@ -300,11 +308,15 @@ unsigned M68kInstrInfo::insertBranch(
unsigned Count = 0;
M68k::CondCode CC = (M68k::CondCode)Cond[0].getImm();
unsigned Opc = GetCondBranchFromCond(CC);
- BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
+ MachineInstr *CondMI = BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*CondMI);
++Count;
if (!FallThru) {
// Two-way Conditional branch. Insert the second branch.
- BuildMI(&MBB, DL, get(M68k::BRA8)).addMBB(FBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(M68k::BRA8)).addMBB(FBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
++Count;
}
return Count;
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.h b/llvm/lib/Target/M68k/M68kInstrInfo.h
index 577967f2fdfc97d..93e69cb81737ca3 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.h
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.h
@@ -261,13 +261,13 @@ class M68kInstrInfo : public M68kGenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
index 74057165166439f..dcb46069247e564 100644
--- a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
+++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
@@ -17,6 +17,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
@@ -104,7 +105,8 @@ void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
unsigned MSP430InstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+ int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.end();
@@ -121,6 +123,8 @@ unsigned MSP430InstrInfo::removeBranch(MachineBasicBlock &MBB,
I->getOpcode() != MSP430::Bm)
break;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
++Count;
@@ -254,8 +258,8 @@ unsigned MSP430InstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) &&
@@ -265,18 +269,25 @@ unsigned MSP430InstrInfo::insertBranch(MachineBasicBlock &MBB,
if (Cond.empty()) {
// Unconditional branch?
assert(!FBB && "Unconditional branch with multiple successors!");
- BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 1;
}
// Conditional branch.
unsigned Count = 0;
- BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
+ MachineInstr *CondBr =
+ BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*CondBr);
++Count;
if (FBB) {
// Two-way Conditional branch. Insert the second branch.
- BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
+ MachineInstr *UncondBr = BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*UncondBr);
++Count;
}
return Count;
diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.h b/llvm/lib/Target/MSP430/MSP430InstrInfo.h
index b8d015a21cd1506..8781a77902ad736 100644
--- a/llvm/lib/Target/MSP430/MSP430InstrInfo.h
+++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.h
@@ -61,12 +61,12 @@ class MSP430InstrInfo : public MSP430GenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
int64_t getFramePoppedByCallee(const MachineInstr &I) const {
assert(isFrameInstr(I) && "Not a frame instruction");
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
index 392cc15d7943afa..d7e0250ca567c77 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
@@ -21,6 +21,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugInfoMetadata.h"
@@ -118,7 +119,8 @@ bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
const DebugLoc &DL,
- ArrayRef<MachineOperand> Cond) const {
+ ArrayRef<MachineOperand> Cond,
+ SlotIndexes *Indexes) const {
unsigned Opc = Cond[0].getImm();
const MCInstrDesc &MCID = get(Opc);
MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
@@ -129,14 +131,16 @@ void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MIB.add(Cond[i]);
}
MIB.addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MIB);
}
unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert(!BytesAdded && "code size not handled");
@@ -151,22 +155,26 @@ unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
// Two-way Conditional branch.
if (FBB) {
- BuildCondBr(MBB, TBB, DL, Cond);
- BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
+ BuildCondBr(MBB, TBB, DL, Cond, Indexes);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 2;
}
// One way branch.
// Unconditional branch.
- if (Cond.empty())
- BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
- else // Conditional branch.
- BuildCondBr(MBB, TBB, DL, Cond);
+ if (Cond.empty()) {
+ MachineInstr *MI = BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
+ } else // Conditional branch.
+ BuildCondBr(MBB, TBB, DL, Cond, Indexes);
return 1;
}
-unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
@@ -183,6 +191,8 @@ unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
if (!getAnalyzableBrOpc(I->getOpcode()))
break;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.rbegin();
++removed;
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.h b/llvm/lib/Target/Mips/MipsInstrInfo.h
index dc4b9d99b39d2a3..4d6c15f11f6d474 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.h
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.h
@@ -65,13 +65,13 @@ class MipsInstrInfo : public MipsGenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
@@ -206,7 +206,8 @@ class MipsInstrInfo : public MipsGenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond) const;
void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
- const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
+ const DebugLoc &DL, ArrayRef<MachineOperand> Cond,
+ SlotIndexes *Indexes = nullptr) const;
};
/// Create MipsInstrInfo objects.
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
index b0d792b5ee3fe69..03280ce24947164 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
@@ -17,6 +17,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/IR/Function.h"
using namespace llvm;
@@ -146,8 +147,8 @@ bool NVPTXInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
return true;
}
-unsigned NVPTXInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned NVPTXInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin())
@@ -157,6 +158,8 @@ unsigned NVPTXInstrInfo::removeBranch(MachineBasicBlock &MBB,
return 0;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
@@ -168,6 +171,8 @@ unsigned NVPTXInstrInfo::removeBranch(MachineBasicBlock &MBB,
return 1;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
return 2;
}
@@ -176,8 +181,8 @@ unsigned NVPTXInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
assert(!BytesAdded && "code size not handled");
// Shouldn't be a fall through.
@@ -187,15 +192,23 @@ unsigned NVPTXInstrInfo::insertBranch(MachineBasicBlock &MBB,
// One-way branch.
if (!FBB) {
+ MachineInstr *MI;
if (Cond.empty()) // Unconditional branch
- BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
+ MI = BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
else // Conditional branch
- BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB);
+ MI = BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 1;
}
// Two-way Conditional Branch.
- BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB);
- BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
+ MachineInstr *CondBr =
+ BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB);
+ MachineInstr *UncondBr = BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
+ if (Indexes) {
+ Indexes->insertMachineInstrInMaps(*CondBr);
+ Indexes->insertMachineInstrInMaps(*UncondBr);
+ }
return 2;
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
index cd068a0939300e7..ef28370f564e0bb 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
@@ -60,12 +60,12 @@ class NVPTXInstrInfo : public NVPTXGenInstrInfo {
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
};
} // namespace llvm
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 6ca68ecdcc773df..37c50362d544adb 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1440,8 +1440,8 @@ bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
return true;
}
-unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
@@ -1455,6 +1455,8 @@ unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB,
return 0;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
@@ -1468,6 +1470,8 @@ unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB,
return 1;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
return 2;
}
@@ -1476,8 +1480,8 @@ unsigned PPCInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) &&
@@ -1488,39 +1492,49 @@ unsigned PPCInstrInfo::insertBranch(MachineBasicBlock &MBB,
// One-way branch.
if (!FBB) {
+ MachineInstr *MI;
if (Cond.empty()) // Unconditional branch
- BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
+ MI = BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
- BuildMI(&MBB, DL, get(Cond[0].getImm() ?
- (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
- (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
+ MI = BuildMI(&MBB, DL,
+ get(Cond[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
+ : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)))
+ .addMBB(TBB);
else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
- BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
+ MI = BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
- BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
+ MI = BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
else // Conditional branch
- BuildMI(&MBB, DL, get(PPC::BCC))
- .addImm(Cond[0].getImm())
- .add(Cond[1])
- .addMBB(TBB);
+ MI = BuildMI(&MBB, DL, get(PPC::BCC))
+ .addImm(Cond[0].getImm())
+ .add(Cond[1])
+ .addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 1;
}
// Two-way Conditional Branch.
+ MachineInstr *CondBr;
if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
- BuildMI(&MBB, DL, get(Cond[0].getImm() ?
- (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
- (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
+ CondBr = BuildMI(&MBB, DL,
+ get(Cond[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
+ : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)))
+ .addMBB(TBB);
else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
- BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
+ CondBr = BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
- BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
+ CondBr = BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
else
- BuildMI(&MBB, DL, get(PPC::BCC))
- .addImm(Cond[0].getImm())
- .add(Cond[1])
- .addMBB(TBB);
- BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
+ CondBr = BuildMI(&MBB, DL, get(PPC::BCC))
+ .addImm(Cond[0].getImm())
+ .add(Cond[1])
+ .addMBB(TBB);
+ MachineInstr *UncondBr = BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
+ if (Indexes) {
+ Indexes->insertMachineInstrInMaps(*CondBr);
+ Indexes->insertMachineInstrInMaps(*UncondBr);
+ }
return 2;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 93d2a58aa39023a..3edebfda4ef7dd7 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -395,12 +395,12 @@ class PPCInstrInfo : public PPCGenInstrInfo {
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
// Select analysis.
bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 14f1bff4aee4ca8..a890b120592741d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -923,8 +923,8 @@ bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
return true;
}
-unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
if (BytesRemoved)
*BytesRemoved = 0;
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
@@ -938,6 +938,8 @@ unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
// Remove the branch.
if (BytesRemoved)
*BytesRemoved += getInstSizeInBytes(*I);
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
@@ -951,15 +953,20 @@ unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
// Remove the branch.
if (BytesRemoved)
*BytesRemoved += getInstSizeInBytes(*I);
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
return 2;
}
// Inserts a branch into the end of the specific MachineBasicBlock, returning
// the number of instructions inserted.
-unsigned RISCVInstrInfo::insertBranch(
- MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
- ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
+unsigned RISCVInstrInfo::insertBranch(MachineBasicBlock &MBB,
+ MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond,
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
if (BytesAdded)
*BytesAdded = 0;
@@ -973,6 +980,8 @@ unsigned RISCVInstrInfo::insertBranch(
MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(MI);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(MI);
return 1;
}
@@ -982,6 +991,8 @@ unsigned RISCVInstrInfo::insertBranch(
*BuildMI(&MBB, DL, getBrCond(CC)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(CondMI);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(CondMI);
// One-way conditional branch.
if (!FBB)
@@ -991,6 +1002,8 @@ unsigned RISCVInstrInfo::insertBranch(
MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(MI);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(MI);
return 2;
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 99c907a98121ae3..ef7672b9ab6d367 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -102,16 +102,16 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &dl,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &dl, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
void insertIndirectBranch(MachineBasicBlock &MBB,
MachineBasicBlock &NewDestBB,
MachineBasicBlock &RestoreBB, const DebugLoc &DL,
int64_t BrOffset, RegScavenger *RS) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
index 42317453a2370e1..ea51c3bd18e8250 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
@@ -200,8 +200,8 @@ bool SPIRVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
// returns the number of instructions that were removed.
// If \p BytesRemoved is non-null, report the change in code size from the
// removed instructions.
-unsigned SPIRVInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned SPIRVInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
report_fatal_error("Branch removal not supported, as MBB info not propagated"
" to OpPhi instructions. Try using -O0 instead.");
}
@@ -219,9 +219,12 @@ unsigned SPIRVInstrInfo::removeBranch(MachineBasicBlock &MBB,
//
// The CFG information in MBB.Predecessors and MBB.Successors must be valid
// before calling this function.
-unsigned SPIRVInstrInfo::insertBranch(
- MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
- ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
+unsigned SPIRVInstrInfo::insertBranch(MachineBasicBlock &MBB,
+ MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond,
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
report_fatal_error("Branch insertion not supported, as MBB info not "
"propagated to OpPhi instructions. Try using "
"-O0 instead.");
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
index c01e30e109bd5b9..8fd1a673d693a86 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
@@ -41,13 +41,13 @@ class SPIRVInstrInfo : public SPIRVGenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
index 90662cd87dcf12f..a4512848edcbfb8 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -20,6 +20,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
@@ -328,29 +329,34 @@ unsigned SparcInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() <= 3) &&
"Sparc branch conditions should have at most three components!");
if (Cond.empty()) {
assert(!FBB && "Unconditional branch with multiple successors!");
- BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
if (BytesAdded)
*BytesAdded = 8;
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 1;
}
// Conditional branch
+ MachineInstr *CondMI;
unsigned Opc = Cond[0].getImm();
unsigned CC = Cond[1].getImm();
if (isRegCondBranchOpcode(Opc)) {
Register Reg = Cond[2].getReg();
- BuildMI(&MBB, DL, get(Opc)).addMBB(TBB).addImm(CC).addReg(Reg);
+ CondMI = BuildMI(&MBB, DL, get(Opc)).addMBB(TBB).addImm(CC).addReg(Reg);
} else {
- BuildMI(&MBB, DL, get(Opc)).addMBB(TBB).addImm(CC);
+ CondMI = BuildMI(&MBB, DL, get(Opc)).addMBB(TBB).addImm(CC);
}
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*CondMI);
if (!FBB) {
if (BytesAdded)
@@ -358,14 +364,17 @@ unsigned SparcInstrInfo::insertBranch(MachineBasicBlock &MBB,
return 1;
}
- BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
if (BytesAdded)
*BytesAdded = 16;
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
+
return 2;
}
-unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
MachineBasicBlock::iterator I = MBB.end();
unsigned Count = 0;
int Removed = 0;
@@ -380,6 +389,8 @@ unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB,
break; // Not a branch
Removed += getInstSizeInBytes(*I);
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
++Count;
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.h b/llvm/lib/Target/Sparc/SparcInstrInfo.h
index 7056d6babe17b93..ecf3af842279ec5 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.h
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.h
@@ -71,13 +71,13 @@ class SparcInstrInfo : public SparcGenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index ac8c395f9064fb8..807e049271cf4eb 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -447,7 +447,8 @@ bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
}
unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+ int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "code size not handled");
// Most of the code and comments here are boilerplate.
@@ -464,6 +465,8 @@ unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB,
break;
// Remove the branch.
I->eraseFromParent();
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I = MBB.end();
++Count;
}
@@ -482,8 +485,8 @@ unsigned SystemZInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
// In this function we output 32-bit branches, which should always
// have enough range. They can be shortened and relaxed by later code
// in the pipeline, if desired.
@@ -497,7 +500,9 @@ unsigned SystemZInstrInfo::insertBranch(MachineBasicBlock &MBB,
if (Cond.empty()) {
// Unconditional branch?
assert(!FBB && "Unconditional branch with multiple successors!");
- BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 1;
}
@@ -505,14 +510,20 @@ unsigned SystemZInstrInfo::insertBranch(MachineBasicBlock &MBB,
unsigned Count = 0;
unsigned CCValid = Cond[0].getImm();
unsigned CCMask = Cond[1].getImm();
- BuildMI(&MBB, DL, get(SystemZ::BRC))
- .addImm(CCValid).addImm(CCMask).addMBB(TBB);
+ MachineInstr *TrueMI = BuildMI(&MBB, DL, get(SystemZ::BRC))
+ .addImm(CCValid)
+ .addImm(CCMask)
+ .addMBB(TBB);
++Count;
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*TrueMI);
if (FBB) {
// Two-way Conditional branch. Insert the second branch.
- BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
+ MachineInstr *FalseMI = BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
++Count;
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*FalseMI);
}
return Count;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
index bb883ea464d376f..f95de9f8eb151f9 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
@@ -238,12 +238,12 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
Register &SrcReg2, int64_t &Mask,
int64_t &Value) const override;
diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp b/llvm/lib/Target/VE/VEInstrInfo.cpp
index ebb9e21389c37b2..5a6815390cfa8f5 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.cpp
+++ b/llvm/lib/Target/VE/VEInstrInfo.cpp
@@ -20,6 +20,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
@@ -227,7 +228,8 @@ unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 3 || Cond.size() == 0) &&
"VE branch conditions should have three component!");
@@ -235,8 +237,9 @@ unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB,
if (Cond.empty()) {
// Uncondition branch
assert(!FBB && "Unconditional branch with multiple successors!");
- BuildMI(&MBB, DL, get(VE::BRCFLa_t))
- .addMBB(TBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(VE::BRCFLa_t)).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 1;
}
@@ -266,30 +269,35 @@ unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB,
opc[1] = VE::BRCFDrr;
}
}
+ MachineInstr *CondMI;
if (Cond[1].isImm()) {
- BuildMI(&MBB, DL, get(opc[0]))
- .add(Cond[0]) // condition code
- .add(Cond[1]) // lhs
- .add(Cond[2]) // rhs
- .addMBB(TBB);
+ CondMI = BuildMI(&MBB, DL, get(opc[0]))
+ .add(Cond[0]) // condition code
+ .add(Cond[1]) // lhs
+ .add(Cond[2]) // rhs
+ .addMBB(TBB);
} else {
- BuildMI(&MBB, DL, get(opc[1]))
- .add(Cond[0])
- .add(Cond[1])
- .add(Cond[2])
- .addMBB(TBB);
+ CondMI = BuildMI(&MBB, DL, get(opc[1]))
+ .add(Cond[0])
+ .add(Cond[1])
+ .add(Cond[2])
+ .addMBB(TBB);
}
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*CondMI);
if (!FBB)
return 1;
- BuildMI(&MBB, DL, get(VE::BRCFLa_t))
- .addMBB(FBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(VE::BRCFLa_t)).addMBB(FBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
+
return 2;
}
-unsigned VEInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned VEInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.end();
@@ -304,6 +312,8 @@ unsigned VEInstrInfo::removeBranch(MachineBasicBlock &MBB,
!isCondBranchOpcode(I->getOpcode()))
break; // Not a branch
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
++Count;
diff --git a/llvm/lib/Target/VE/VEInstrInfo.h b/llvm/lib/Target/VE/VEInstrInfo.h
index 4fe56f24116f8cc..d081e29c6e1e7a9 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.h
+++ b/llvm/lib/Target/VE/VEInstrInfo.h
@@ -67,13 +67,13 @@ class VEInstrInfo : public VEGenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
index 32a4accd040ebe9..e3bf8d3f465c5cb 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
@@ -22,6 +22,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
using namespace llvm;
#define DEBUG_TYPE "wasm-instr-info"
@@ -135,7 +136,8 @@ bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
}
unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+ int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::instr_iterator I = MBB.instr_end();
@@ -148,6 +150,8 @@ unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB,
if (!I->isTerminator())
break;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.instr_end();
++Count;
@@ -156,29 +160,42 @@ unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB,
return Count;
}
-unsigned WebAssemblyInstrInfo::insertBranch(
- MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
- ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
+unsigned WebAssemblyInstrInfo::insertBranch(MachineBasicBlock &MBB,
+ MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond,
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
assert(!BytesAdded && "code size not handled");
if (Cond.empty()) {
if (!TBB)
return 0;
- BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 1;
}
assert(Cond.size() == 2 && "Expected a flag and a successor block");
- if (Cond[0].getImm())
- BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
- else
- BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
+ MachineInstr *CondMI;
+ if (Cond[0].getImm()) {
+ CondMI =
+ BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
+ } else {
+ CondMI =
+ BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
+ }
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*CondMI);
if (!FBB)
return 1;
- BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 2;
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
index c1e1a790c60e2cd..d37a13e08f53d43 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
@@ -56,12 +56,12 @@ class WebAssemblyInstrInfo final : public WebAssemblyGenInstrInfo {
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 205fd24e6d40295..6be50987e7da3a7 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3342,8 +3342,8 @@ bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
return true;
}
-unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.end();
@@ -3357,6 +3357,8 @@ unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
X86::getCondFromBranch(*I) == X86::COND_INVALID)
break;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
++Count;
@@ -3369,8 +3371,8 @@ unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) &&
@@ -3380,7 +3382,9 @@ unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
if (Cond.empty()) {
// Unconditional branch?
assert(!FBB && "Unconditional branch with multiple successors!");
- BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
+ MachineInstr *MI = BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 1;
}
@@ -3388,15 +3392,15 @@ unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
bool FallThru = FBB == nullptr;
// Conditional branch.
- unsigned Count = 0;
+ SmallVector<MachineInstr *> Instrs;
X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
switch (CC) {
case X86::COND_NE_OR_P:
// Synthesize NE_OR_P with two branches.
- BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
- ++Count;
- BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
- ++Count;
+ Instrs.push_back(
+ BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE));
+ Instrs.push_back(
+ BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P));
break;
case X86::COND_E_AND_NP:
// Use the next block of MBB as FBB if it is null.
@@ -3406,22 +3410,24 @@ unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
"body is a fall-through.");
}
// Synthesize COND_E_AND_NP with two branches.
- BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
- ++Count;
- BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
- ++Count;
+ Instrs.push_back(
+ BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE));
+ Instrs.push_back(
+ BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP));
break;
default: {
- BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
- ++Count;
+ Instrs.push_back(BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC));
}
}
if (!FallThru) {
// Two-way Conditional branch. Insert the second branch.
- BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
- ++Count;
+ Instrs.push_back(BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB));
}
- return Count;
+ if (Indexes) {
+ for (MachineInstr *MI : Instrs)
+ Indexes->insertMachineInstrInMaps(*MI);
+ }
+ return Instrs.size();
}
bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 9a072c6569fe978..d1bd30059d88dfc 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -349,12 +349,12 @@ class X86InstrInfo final : public X86GenInstrInfo {
TargetInstrInfo::MachineBranchPredicate &MBP,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
Register, Register, Register, int &, int &,
int &) const override;
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
index d8a8e2cddf15411..8acd22ad2e144a1 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -18,6 +18,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCContext.h"
@@ -272,8 +273,8 @@ unsigned XCoreInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
+ const DebugLoc &DL, int *BytesAdded,
+ SlotIndexes *Indexes) const {
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) &&
@@ -281,29 +282,35 @@ unsigned XCoreInstrInfo::insertBranch(MachineBasicBlock &MBB,
assert(!BytesAdded && "code size not handled");
if (!FBB) { // One way branch.
+ MachineInstr *MI;
if (Cond.empty()) {
// Unconditional branch
- BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
+ MI = BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
} else {
// Conditional branch.
unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
- BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
- .addMBB(TBB);
+ MI = BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
}
+ if (Indexes)
+ Indexes->insertMachineInstrInMaps(*MI);
return 1;
}
// Two-way Conditional branch.
assert(Cond.size() == 2 && "Unexpected number of components!");
unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
- BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
- .addMBB(TBB);
- BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
+ MachineInstr *CondBr =
+ BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
+ MachineInstr *UncondBr = BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
+ if (Indexes) {
+ Indexes->insertMachineInstrInMaps(*CondBr);
+ Indexes->insertMachineInstrInMaps(*UncondBr);
+ }
return 2;
}
-unsigned
-XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const {
+unsigned XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
+ SlotIndexes *Indexes) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
@@ -314,6 +321,8 @@ XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const {
return 0;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
I = MBB.end();
@@ -324,6 +333,8 @@ XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const {
return 1;
// Remove the branch.
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*I);
I->eraseFromParent();
return 2;
}
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.h b/llvm/lib/Target/XCore/XCoreInstrInfo.h
index 9bf7e2dcccb7d73..a582588638b7a3f 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.h
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.h
@@ -56,11 +56,11 @@ class XCoreInstrInfo : public XCoreGenInstrInfo {
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded = nullptr) const override;
+ const DebugLoc &DL, int *BytesAdded = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
- unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
+ SlotIndexes *Indexes = nullptr) const override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
>From bec43c35d4c2ff578a3b70dda14bffaafb28b567 Mon Sep 17 00:00:00 2001
From: Carl Ritson <carl.ritson at amd.com>
Date: Thu, 14 Sep 2023 16:41:23 +0900
Subject: [PATCH 2/2] Address reviewer feedback.
- Reverse order of Indexes and BytesAdded/BytesRemoved
- Describe new parameters in comments
---
llvm/include/llvm/CodeGen/MachineBasicBlock.h | 12 ++++----
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 24 +++++++++------
llvm/lib/CodeGen/BranchRelaxation.cpp | 8 +++--
llvm/lib/CodeGen/MachineBasicBlock.cpp | 29 +++++++++----------
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 14 ++++-----
llvm/lib/Target/AArch64/AArch64InstrInfo.h | 8 ++---
llvm/lib/Target/AMDGPU/R600InstrInfo.cpp | 9 +++---
llvm/lib/Target/AMDGPU/R600InstrInfo.h | 8 ++---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 8 ++---
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 8 ++---
llvm/lib/Target/ARC/ARCInstrInfo.cpp | 9 +++---
llvm/lib/Target/ARC/ARCInstrInfo.h | 8 ++---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 14 ++++-----
llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 8 ++---
llvm/lib/Target/AVR/AVRInstrInfo.cpp | 9 +++---
llvm/lib/Target/AVR/AVRInstrInfo.h | 8 ++---
llvm/lib/Target/BPF/BPFInstrInfo.cpp | 9 +++---
llvm/lib/Target/BPF/BPFInstrInfo.h | 8 ++---
llvm/lib/Target/CSKY/CSKYInstrInfo.cpp | 9 +++---
llvm/lib/Target/CSKY/CSKYInstrInfo.h | 8 ++---
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 18 +++++-------
llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 8 ++---
llvm/lib/Target/Lanai/LanaiInstrInfo.cpp | 9 +++---
llvm/lib/Target/Lanai/LanaiInstrInfo.h | 8 ++---
.../Target/LoongArch/LoongArchInstrInfo.cpp | 14 ++++-----
.../lib/Target/LoongArch/LoongArchInstrInfo.h | 8 ++---
llvm/lib/Target/M68k/M68kInstrInfo.cpp | 9 +++---
llvm/lib/Target/M68k/M68kInstrInfo.h | 8 ++---
llvm/lib/Target/MSP430/MSP430InstrInfo.cpp | 8 ++---
llvm/lib/Target/MSP430/MSP430InstrInfo.h | 8 ++---
llvm/lib/Target/Mips/MipsInstrInfo.cpp | 9 +++---
llvm/lib/Target/Mips/MipsInstrInfo.h | 8 ++---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp | 9 +++---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.h | 8 ++---
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 9 +++---
llvm/lib/Target/PowerPC/PPCInstrInfo.h | 9 +++---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 9 +++---
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 8 ++---
llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp | 9 +++---
llvm/lib/Target/SPIRV/SPIRVInstrInfo.h | 8 ++---
llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 9 +++---
llvm/lib/Target/Sparc/SparcInstrInfo.h | 8 ++---
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 14 ++++-----
llvm/lib/Target/SystemZ/SystemZInstrInfo.h | 8 ++---
llvm/lib/Target/VE/VEInstrInfo.cpp | 8 ++---
llvm/lib/Target/VE/VEInstrInfo.h | 8 ++---
.../WebAssembly/WebAssemblyInstrInfo.cpp | 14 ++++-----
.../Target/WebAssembly/WebAssemblyInstrInfo.h | 8 ++---
llvm/lib/Target/X86/X86InstrInfo.cpp | 9 +++---
llvm/lib/Target/X86/X86InstrInfo.h | 8 ++---
llvm/lib/Target/XCore/XCoreInstrInfo.cpp | 9 +++---
llvm/lib/Target/XCore/XCoreInstrInfo.h | 8 ++---
52 files changed, 263 insertions(+), 250 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
index 74e7b98ca8a7526..6157f446d5f9620 100644
--- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
@@ -688,11 +688,13 @@ class MachineBasicBlock
}
/// Update the terminator instructions in block to account for changes to
- /// block layout which may have been made. PreviousLayoutSuccessor should be
- /// set to the block which may have been used as fallthrough before the block
- /// layout was modified. If the block previously fell through to that block,
- /// it may now need a branch. If it previously branched to another block, it
- /// may now be able to fallthrough to the current layout successor.
+ /// block layout which may have been made. \p PreviousLayoutSuccessor should
+ /// be set to the block which may have been used as fallthrough before the
+ /// block layout was modified. If the block previously fell through to that
+ /// block, it may now need a branch. If it previously branched to another
+ /// block, it may now be able to fallthrough to the current layout successor.
+ /// SlotIndexes provided by \p Indexes will be updated to reflect any
+ /// instructions inserted or removed.
void updateTerminator(MachineBasicBlock *PreviousLayoutSuccessor,
SlotIndexes *Indexes = nullptr);
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 8d40b8de8535f98..5e902b8385b411a 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -680,19 +680,24 @@ class TargetInstrInfo : public MCInstrInfo {
/// Remove the branching code at the end of the specific MBB.
/// This is only invoked in cases where analyzeBranch returns success. It
/// returns the number of instructions that were removed.
+ /// If \p Indexes is non-null, then instructions will also be removed from
+ /// SlotIndexes.
/// If \p BytesRemoved is non-null, report the change in code size from the
/// removed instructions.
virtual unsigned removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const {
+ SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const {
llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
}
/// Insert branch code into the end of the specified MachineBasicBlock. The
/// operands to this method are the same as those returned by analyzeBranch.
/// This is only invoked in cases where analyzeBranch returns success. It
- /// returns the number of instructions inserted. If \p BytesAdded is non-null,
- /// report the change in code size from the added instructions.
+ /// returns the number of instructions inserted.
+ /// If \p Indexes is non-null, then added instructions will be inserted into
+ /// SlotIndexes.
+ /// If \p BytesAdded is non-null, report the change in code size from the
+ /// added instructions.
///
/// It is also invoked by tail merging to add unconditional branches in
/// cases where analyzeBranch doesn't apply because there was no original
@@ -704,18 +709,19 @@ class TargetInstrInfo : public MCInstrInfo {
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const {
+ const DebugLoc &DL,
+ SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const {
llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
}
unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
MachineBasicBlock *DestBB,
const DebugLoc &DL,
- int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const {
+ SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const {
return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
- BytesAdded, Indexes);
+ Indexes, BytesAdded);
}
/// Object returned by analyzeLoopForPipelining. Allows software pipelining
diff --git a/llvm/lib/CodeGen/BranchRelaxation.cpp b/llvm/lib/CodeGen/BranchRelaxation.cpp
index f50eb5e1730a328..e87d35633eea11b 100644
--- a/llvm/lib/CodeGen/BranchRelaxation.cpp
+++ b/llvm/lib/CodeGen/BranchRelaxation.cpp
@@ -364,7 +364,8 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) {
MachineBasicBlock *DestBB) {
unsigned &BBSize = BlockInfo[MBB->getNumber()].Size;
int NewBrSize = 0;
- TII->insertUnconditionalBranch(*MBB, DestBB, DL, &NewBrSize);
+ TII->insertUnconditionalBranch(*MBB, DestBB, DL, /*Indexes=*/nullptr,
+ &NewBrSize);
BBSize += NewBrSize;
};
auto insertBranch = [&](MachineBasicBlock *MBB, MachineBasicBlock *TBB,
@@ -372,13 +373,14 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) {
SmallVectorImpl<MachineOperand>& Cond) {
unsigned &BBSize = BlockInfo[MBB->getNumber()].Size;
int NewBrSize = 0;
- TII->insertBranch(*MBB, TBB, FBB, Cond, DL, &NewBrSize);
+ TII->insertBranch(*MBB, TBB, FBB, Cond, DL, /*Indexes=*/nullptr,
+ &NewBrSize);
BBSize += NewBrSize;
};
auto removeBranch = [&](MachineBasicBlock *MBB) {
unsigned &BBSize = BlockInfo[MBB->getNumber()].Size;
int RemovedSize = 0;
- TII->removeBranch(*MBB, &RemovedSize);
+ TII->removeBranch(*MBB, /*Indexes=*/nullptr, &RemovedSize);
BBSize -= RemovedSize;
};
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 09df32afb37c00c..45b1a008ad7d2d7 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -701,7 +701,7 @@ void MachineBasicBlock::updateTerminator(
// The block has an unconditional branch. If its successor is now its
// layout successor, delete the branch.
if (isLayoutSuccessor(TBB))
- TII->removeBranch(*this, nullptr, Indexes);
+ TII->removeBranch(*this, Indexes);
} else {
// The block has an unconditional fallthrough, or the end of the block is
// unreachable.
@@ -718,7 +718,7 @@ void MachineBasicBlock::updateTerminator(
// successor, insert a branch to jump to it.
if (!isLayoutSuccessor(PreviousLayoutSuccessor))
TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL,
- nullptr, Indexes);
+ Indexes);
}
return;
}
@@ -730,11 +730,11 @@ void MachineBasicBlock::updateTerminator(
if (isLayoutSuccessor(TBB)) {
if (TII->reverseBranchCondition(Cond))
return;
- TII->removeBranch(*this, nullptr, Indexes);
- TII->insertBranch(*this, FBB, nullptr, Cond, DL, nullptr, Indexes);
+ TII->removeBranch(*this, Indexes);
+ TII->insertBranch(*this, FBB, nullptr, Cond, DL, Indexes);
} else if (isLayoutSuccessor(FBB)) {
- TII->removeBranch(*this, nullptr, Indexes);
- TII->insertBranch(*this, TBB, nullptr, Cond, DL, nullptr, Indexes);
+ TII->removeBranch(*this, Indexes);
+ TII->insertBranch(*this, TBB, nullptr, Cond, DL, Indexes);
}
return;
}
@@ -748,10 +748,10 @@ void MachineBasicBlock::updateTerminator(
// We had a fallthrough to the same basic block as the conditional jump
// targets. Remove the conditional jump, leaving an unconditional
// fallthrough or an unconditional jump.
- TII->removeBranch(*this, nullptr, Indexes);
+ TII->removeBranch(*this, Indexes);
if (!isLayoutSuccessor(TBB)) {
Cond.clear();
- TII->insertBranch(*this, TBB, nullptr, Cond, DL, nullptr, Indexes);
+ TII->insertBranch(*this, TBB, nullptr, Cond, DL, Indexes);
}
return;
}
@@ -762,16 +762,15 @@ void MachineBasicBlock::updateTerminator(
// We can't reverse the condition, add an unconditional branch.
Cond.clear();
TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL,
- nullptr, Indexes);
+ Indexes);
return;
}
- TII->removeBranch(*this, nullptr, Indexes);
+ TII->removeBranch(*this, Indexes);
TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL,
- nullptr, Indexes);
- } else if (!isLayoutSuccessor(PreviousLayoutSuccessor)) {
- TII->removeBranch(*this, nullptr, Indexes);
- TII->insertBranch(*this, TBB, PreviousLayoutSuccessor, Cond, DL, nullptr,
Indexes);
+ } else if (!isLayoutSuccessor(PreviousLayoutSuccessor)) {
+ TII->removeBranch(*this, Indexes);
+ TII->insertBranch(*this, TBB, PreviousLayoutSuccessor, Cond, DL, Indexes);
}
}
@@ -1183,7 +1182,7 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
if (!NMBB->isLayoutSuccessor(Succ)) {
SmallVector<MachineOperand, 4> Cond;
const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
- TII->insertBranch(*NMBB, Succ, nullptr, Cond, DL, nullptr, Indexes);
+ TII->insertBranch(*NMBB, Succ, nullptr, Cond, DL, Indexes);
}
// Fix PHI nodes in Succ so they refer to NMBB instead of this.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 012f56f306f0527..fcd470d7b6d90ef 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -535,8 +535,8 @@ bool AArch64InstrInfo::reverseBranchCondition(
}
unsigned AArch64InstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved,
- SlotIndexes *Indexes) const {
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
if (I == MBB.end())
return 0;
@@ -599,12 +599,10 @@ void AArch64InstrInfo::instantiateCondBranch(MachineBasicBlock &MBB,
}
}
-unsigned AArch64InstrInfo::insertBranch(MachineBasicBlock &MBB,
- MachineBasicBlock *TBB,
- MachineBasicBlock *FBB,
- ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+unsigned AArch64InstrInfo::insertBranch(
+ MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond, const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index cd6fcd32ee8ac11..ba42a1eb1079363 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -225,12 +225,12 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
bool analyzeBranchPredicate(MachineBasicBlock &MBB,
MachineBranchPredicate &MBP,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
index 7d495553e945a7a..7d34187860537bb 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -731,8 +731,8 @@ unsigned R600InstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert(!BytesAdded && "code size not handled");
@@ -782,8 +782,9 @@ unsigned R600InstrInfo::insertBranch(MachineBasicBlock &MBB,
}
}
-unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB,
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
// Note : we leave PRED* instructions there.
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.h b/llvm/lib/Target/AMDGPU/R600InstrInfo.h
index 5557b435f1d0c51..bc9f19d32d068ba 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.h
@@ -170,11 +170,11 @@ class R600InstrInfo final : public R600GenInstrInfo {
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
bool isPredicated(const MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 72ee0a3a6725ee3..3ff192bc79ec8be 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2843,8 +2843,8 @@ bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
return analyzeBranchImpl(MBB, I, TBB, FBB, Cond, AllowModify);
}
-unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes,
+ int *BytesRemoved) const {
unsigned Count = 0;
unsigned RemovedSize = 0;
for (MachineInstr &MI : llvm::make_early_inc_range(MBB.terminators())) {
@@ -2875,8 +2875,8 @@ unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
if (!FBB && Cond.empty()) {
MachineInstr *UncondBr =
BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH)).addMBB(TBB);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 25568845361e584..4915a5777e879bb 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -331,13 +331,13 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
bool reverseBranchCondition(
SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
index 74d36c72f9ee179..202a14efa49baf3 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
@@ -252,8 +252,9 @@ bool ARCInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
return false;
}
-unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "Code size not handled");
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
if (I == MBB.end())
@@ -375,8 +376,8 @@ unsigned ARCInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
assert(!BytesAdded && "Code size not handled.");
// Shouldn't be a fall through.
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.h b/llvm/lib/Target/ARC/ARCInstrInfo.h
index be618e953a9ce36..f176894367ba030 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.h
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.h
@@ -57,11 +57,11 @@ class ARCInstrInfo : public ARCGenInstrInfo {
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &, MCRegister DestReg, MCRegister SrcReg,
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index d9efa39aeadd42f..82a0dc43689b1d8 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -469,8 +469,8 @@ bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
}
unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved,
- SlotIndexes *Indexes) const {
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
@@ -500,12 +500,10 @@ unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB,
return 2;
}
-unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB,
- MachineBasicBlock *TBB,
- MachineBasicBlock *FBB,
- ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+unsigned ARMBaseInstrInfo::insertBranch(
+ MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond, const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
assert(!BytesAdded && "code size not handled");
ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
int BOpc = !AFI->isThumbFunction()
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index c7c3554d9d1bbd0..fa15af35f745f3f 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -143,12 +143,12 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
index b9d0ab552a19d90..3f8802324c1810e 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
@@ -400,8 +400,8 @@ unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
if (BytesAdded)
*BytesAdded = 0;
@@ -444,8 +444,9 @@ unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB,
return Count;
}
-unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB,
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
if (BytesRemoved)
*BytesRemoved = 0;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.h b/llvm/lib/Target/AVR/AVRInstrInfo.h
index 28bd92bb6b5dbd6..50d41b9ac346f49 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.h
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.h
@@ -99,10 +99,10 @@ class AVRInstrInfo : public AVRGenInstrInfo {
bool AllowModify = false) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInstrInfo.cpp
index afb513a6c8e2e35..31619e40b6214c4 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.cpp
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.cpp
@@ -222,8 +222,8 @@ unsigned BPFInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
assert(!BytesAdded && "code size not handled");
// Shouldn't be a fall through.
@@ -241,8 +241,9 @@ unsigned BPFInstrInfo::insertBranch(MachineBasicBlock &MBB,
llvm_unreachable("Unexpected conditional branch");
}
-unsigned BPFInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned BPFInstrInfo::removeBranch(MachineBasicBlock &MBB,
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.end();
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.h b/llvm/lib/Target/BPF/BPFInstrInfo.h
index 1594babeb2ebfe0..34be9799bff95d5 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.h
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.h
@@ -52,12 +52,12 @@ class BPFInstrInfo : public BPFGenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
private:
void expandMEMCPY(MachineBasicBlock::iterator) const;
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
index cd1a148e7c010fe..679efeb4c73d188 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
@@ -111,8 +111,9 @@ bool CSKYInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
return true;
}
-unsigned CSKYInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned CSKYInstrInfo::removeBranch(MachineBasicBlock &MBB,
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
if (BytesRemoved)
*BytesRemoved = 0;
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
@@ -160,8 +161,8 @@ unsigned CSKYInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
if (BytesAdded)
*BytesAdded = 0;
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.h b/llvm/lib/Target/CSKY/CSKYInstrInfo.h
index 43e7f7a3fbb00c9..45fce296e326f6d 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.h
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.h
@@ -59,16 +59,16 @@ class CSKYInstrInfo : public CSKYGenInstrInfo {
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index ccee614e783a828..2c7526d821d6f6e 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -604,8 +604,8 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
}
unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved,
- SlotIndexes *Indexes) const {
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
@@ -629,12 +629,10 @@ unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
return Count;
}
-unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
- MachineBasicBlock *TBB,
- MachineBasicBlock *FBB,
- ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+unsigned HexagonInstrInfo::insertBranch(
+ MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond, const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
unsigned BOpc = Hexagon::J2_jump;
unsigned BccOpc = Hexagon::J2_jumpt;
assert(validateBranchCond(Cond) && "Invalid branching condition");
@@ -660,8 +658,8 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
!analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
reverseBranchCondition(Cond);
- removeBranch(MBB, nullptr, Indexes);
- return insertBranch(MBB, TBB, nullptr, Cond, DL, nullptr, Indexes);
+ removeBranch(MBB, Indexes);
+ return insertBranch(MBB, TBB, nullptr, Cond, DL, Indexes);
}
MachineInstr *MI = BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
if (Indexes)
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index f444ec873ebf5bf..ea04a966368d374 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -111,8 +111,8 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
/// Remove the branching code at the end of the specific MBB.
/// This is only invoked in cases where analyzeBranch returns success. It
/// returns the number of instructions that were removed.
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
/// Insert branch code into the end of the specified MachineBasicBlock.
/// The operands to this method are the same as those
@@ -126,8 +126,8 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
/// merging needs to be disabled.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
/// Analyze loop L, which must be a single-basic-block loop, and if the
/// conditions can be understood enough produce a PipelinerLoopInfo object.
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
index ec079453735be01..89a1f22ac85c85a 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
@@ -658,8 +658,8 @@ unsigned LanaiInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TrueBlock,
MachineBasicBlock *FalseBlock,
ArrayRef<MachineOperand> Condition,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
// Shouldn't be a fall through.
assert(TrueBlock && "insertBranch must not be told to insert a fallthrough");
assert(!BytesAdded && "code size not handled");
@@ -694,8 +694,9 @@ unsigned LanaiInstrInfo::insertBranch(MachineBasicBlock &MBB,
return 2;
}
-unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB,
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator Instruction = MBB.end();
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.h b/llvm/lib/Target/Lanai/LanaiInstrInfo.h
index a90f47eb37595f6..5d66056a0f556ec 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.h
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.h
@@ -89,8 +89,8 @@ class LanaiInstrInfo : public LanaiGenInstrInfo {
SmallVectorImpl<MachineOperand> &Condition,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
// For a comparison instruction, return the source registers in SrcReg and
// SrcReg2 if having two register operands, and the value it compares against
@@ -139,8 +139,8 @@ class LanaiInstrInfo : public LanaiGenInstrInfo {
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock,
MachineBasicBlock *FalseBlock,
ArrayRef<MachineOperand> Condition, const DebugLoc &DL,
- int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
};
static inline bool isSPLSOpcode(unsigned Opcode) {
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
index 79eea5d328897ce..fc4e2d8b1e84f11 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
@@ -320,8 +320,8 @@ bool LoongArchInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
}
unsigned LoongArchInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved,
- SlotIndexes *Indexes) const {
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
if (BytesRemoved)
*BytesRemoved = 0;
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
@@ -357,12 +357,10 @@ unsigned LoongArchInstrInfo::removeBranch(MachineBasicBlock &MBB,
// Inserts a branch into the end of the specific MachineBasicBlock, returning
// the number of instructions inserted.
-unsigned LoongArchInstrInfo::insertBranch(MachineBasicBlock &MBB,
- MachineBasicBlock *TBB,
- MachineBasicBlock *FBB,
- ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+unsigned LoongArchInstrInfo::insertBranch(
+ MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond, const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
if (BytesAdded)
*BytesAdded = 0;
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
index 539ef9c8387448f..08b9c88bbdb8162 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
@@ -62,13 +62,13 @@ class LoongArchInstrInfo : public LoongArchGenInstrInfo {
bool isBranchOffsetInRange(unsigned BranchOpc,
int64_t BrOffset) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &dl, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
void insertIndirectBranch(MachineBasicBlock &MBB,
MachineBasicBlock &NewDestBB,
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
index 4fd3ff84a30a45f..82e60ea6adcf198 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -255,8 +255,9 @@ bool M68kInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, AllowModify);
}
-unsigned M68kInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned M68kInstrInfo::removeBranch(MachineBasicBlock &MBB,
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.end();
@@ -284,8 +285,8 @@ unsigned M68kInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
// Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) &&
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.h b/llvm/lib/Target/M68k/M68kInstrInfo.h
index 93e69cb81737ca3..2a6e720c71d225e 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.h
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.h
@@ -261,13 +261,13 @@ class M68kInstrInfo : public M68kGenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
index dcb46069247e564..835dc9a8ccaaee3 100644
--- a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
+++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
@@ -105,8 +105,8 @@ void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
unsigned MSP430InstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved,
- SlotIndexes *Indexes) const {
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.end();
@@ -258,8 +258,8 @@ unsigned MSP430InstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) &&
diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.h b/llvm/lib/Target/MSP430/MSP430InstrInfo.h
index 8781a77902ad736..42ec12d9376effa 100644
--- a/llvm/lib/Target/MSP430/MSP430InstrInfo.h
+++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.h
@@ -61,12 +61,12 @@ class MSP430InstrInfo : public MSP430GenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
int64_t getFramePoppedByCallee(const MachineInstr &I) const {
assert(isFrameInstr(I) && "Not a frame instruction");
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
index d7e0250ca567c77..ab74ffb61b0dbc2 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
@@ -139,8 +139,8 @@ unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert(!BytesAdded && "code size not handled");
@@ -173,8 +173,9 @@ unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
return 1;
}
-unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.h b/llvm/lib/Target/Mips/MipsInstrInfo.h
index 4d6c15f11f6d474..bf9c7f5c78279e3 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.h
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.h
@@ -65,13 +65,13 @@ class MipsInstrInfo : public MipsGenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
index 03280ce24947164..298599229eec37d 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
@@ -147,8 +147,9 @@ bool NVPTXInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
return true;
}
-unsigned NVPTXInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned NVPTXInstrInfo::removeBranch(MachineBasicBlock &MBB,
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin())
@@ -181,8 +182,8 @@ unsigned NVPTXInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
assert(!BytesAdded && "code size not handled");
// Shouldn't be a fall through.
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
index ef28370f564e0bb..0e8f9bd0f4775cd 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
@@ -60,12 +60,12 @@ class NVPTXInstrInfo : public NVPTXGenInstrInfo {
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
};
} // namespace llvm
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 37c50362d544adb..1ff163f73b3de86 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1440,8 +1440,9 @@ bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
return true;
}
-unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB,
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
@@ -1480,8 +1481,8 @@ unsigned PPCInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) &&
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 3edebfda4ef7dd7..d102b82d8a6410e 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -395,12 +395,13 @@ class PPCInstrInfo : public PPCGenInstrInfo {
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
// Select analysis.
bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index a890b120592741d..30c29360b9c9c02 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -923,8 +923,9 @@ bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
return true;
}
-unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
if (BytesRemoved)
*BytesRemoved = 0;
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
@@ -965,8 +966,8 @@ unsigned RISCVInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
if (BytesAdded)
*BytesAdded = 0;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index ef7672b9ab6d367..0964eddd40a83f2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -102,16 +102,16 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &dl, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
void insertIndirectBranch(MachineBasicBlock &MBB,
MachineBasicBlock &NewDestBB,
MachineBasicBlock &RestoreBB, const DebugLoc &DL,
int64_t BrOffset, RegScavenger *RS) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
index ea51c3bd18e8250..313d26d9f652666 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
@@ -200,8 +200,9 @@ bool SPIRVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
// returns the number of instructions that were removed.
// If \p BytesRemoved is non-null, report the change in code size from the
// removed instructions.
-unsigned SPIRVInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned SPIRVInstrInfo::removeBranch(MachineBasicBlock &MBB,
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
report_fatal_error("Branch removal not supported, as MBB info not propagated"
" to OpPhi instructions. Try using -O0 instead.");
}
@@ -223,8 +224,8 @@ unsigned SPIRVInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
report_fatal_error("Branch insertion not supported, as MBB info not "
"propagated to OpPhi instructions. Try using "
"-O0 instead.");
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
index 8fd1a673d693a86..02050023975b251 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
@@ -41,13 +41,13 @@ class SPIRVInstrInfo : public SPIRVGenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
index a4512848edcbfb8..dad5fee070d0d4f 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -329,8 +329,8 @@ unsigned SparcInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() <= 3) &&
"Sparc branch conditions should have at most three components!");
@@ -373,8 +373,9 @@ unsigned SparcInstrInfo::insertBranch(MachineBasicBlock &MBB,
return 2;
}
-unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB,
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
MachineBasicBlock::iterator I = MBB.end();
unsigned Count = 0;
int Removed = 0;
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.h b/llvm/lib/Target/Sparc/SparcInstrInfo.h
index ecf3af842279ec5..9fc41d551413d03 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.h
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.h
@@ -71,13 +71,13 @@ class SparcInstrInfo : public SparcGenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 807e049271cf4eb..b8958909a472022 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -447,8 +447,8 @@ bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
}
unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved,
- SlotIndexes *Indexes) const {
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
// Most of the code and comments here are boilerplate.
@@ -481,12 +481,10 @@ reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
return false;
}
-unsigned SystemZInstrInfo::insertBranch(MachineBasicBlock &MBB,
- MachineBasicBlock *TBB,
- MachineBasicBlock *FBB,
- ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+unsigned SystemZInstrInfo::insertBranch(
+ MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond, const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
// In this function we output 32-bit branches, which should always
// have enough range. They can be shortened and relaxed by later code
// in the pipeline, if desired.
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
index f95de9f8eb151f9..e4c016ff186ced5 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
@@ -238,12 +238,12 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
Register &SrcReg2, int64_t &Mask,
int64_t &Value) const override;
diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp b/llvm/lib/Target/VE/VEInstrInfo.cpp
index 5a6815390cfa8f5..35712125e053578 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.cpp
+++ b/llvm/lib/Target/VE/VEInstrInfo.cpp
@@ -228,8 +228,8 @@ unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 3 || Cond.size() == 0) &&
"VE branch conditions should have three component!");
@@ -296,8 +296,8 @@ unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB,
return 2;
}
-unsigned VEInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned VEInstrInfo::removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.end();
diff --git a/llvm/lib/Target/VE/VEInstrInfo.h b/llvm/lib/Target/VE/VEInstrInfo.h
index d081e29c6e1e7a9..b9d6306f34770fb 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.h
+++ b/llvm/lib/Target/VE/VEInstrInfo.h
@@ -67,13 +67,13 @@ class VEInstrInfo : public VEGenInstrInfo {
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
index e3bf8d3f465c5cb..bed6a325c775ed4 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
@@ -136,8 +136,8 @@ bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
}
unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved,
- SlotIndexes *Indexes) const {
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::instr_iterator I = MBB.instr_end();
@@ -160,12 +160,10 @@ unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB,
return Count;
}
-unsigned WebAssemblyInstrInfo::insertBranch(MachineBasicBlock &MBB,
- MachineBasicBlock *TBB,
- MachineBasicBlock *FBB,
- ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+unsigned WebAssemblyInstrInfo::insertBranch(
+ MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond, const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
assert(!BytesAdded && "code size not handled");
if (Cond.empty()) {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
index d37a13e08f53d43..bd671a3ae4c6ad0 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
@@ -56,12 +56,12 @@ class WebAssemblyInstrInfo final : public WebAssemblyGenInstrInfo {
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 6be50987e7da3a7..a5380c47e56e65f 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3342,8 +3342,9 @@ bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
return true;
}
-unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.end();
@@ -3371,8 +3372,8 @@ unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) &&
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index d1bd30059d88dfc..2ab3e3093b600ba 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -349,12 +349,12 @@ class X86InstrInfo final : public X86GenInstrInfo {
TargetInstrInfo::MachineBranchPredicate &MBP,
bool AllowModify = false) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
Register, Register, Register, int &, int &,
int &) const override;
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
index 8acd22ad2e144a1..3b92d40d1c2d4ff 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -273,8 +273,8 @@ unsigned XCoreInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded,
- SlotIndexes *Indexes) const {
+ const DebugLoc &DL, SlotIndexes *Indexes,
+ int *BytesAdded) const {
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) &&
@@ -309,8 +309,9 @@ unsigned XCoreInstrInfo::insertBranch(MachineBasicBlock &MBB,
return 2;
}
-unsigned XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved,
- SlotIndexes *Indexes) const {
+unsigned XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB,
+ SlotIndexes *Indexes,
+ int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.h b/llvm/lib/Target/XCore/XCoreInstrInfo.h
index a582588638b7a3f..461f11a0645d28f 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.h
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.h
@@ -56,11 +56,11 @@ class XCoreInstrInfo : public XCoreGenInstrInfo {
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL, int *BytesAdded = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ const DebugLoc &DL, SlotIndexes *Indexes = nullptr,
+ int *BytesAdded = nullptr) const override;
- unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr,
- SlotIndexes *Indexes = nullptr) const override;
+ unsigned removeBranch(MachineBasicBlock &MBB, SlotIndexes *Indexes = nullptr,
+ int *BytesRemoved = nullptr) const override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
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