[llvm] 86735a4 - reland [InlineAsm] wrap ConstraintCode in enum class NFC (#66264)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 13 13:31:29 PDT 2023
Author: Nick Desaulniers
Date: 2023-09-13T13:31:24-07:00
New Revision: 86735a4353aee4a3ba1e2feea173a7cc659c7a60
URL: https://github.com/llvm/llvm-project/commit/86735a4353aee4a3ba1e2feea173a7cc659c7a60
DIFF: https://github.com/llvm/llvm-project/commit/86735a4353aee4a3ba1e2feea173a7cc659c7a60.diff
LOG: reland [InlineAsm] wrap ConstraintCode in enum class NFC (#66264)
reland [InlineAsm] wrap ConstraintCode in enum class NFC (#66003)
This reverts commit ee643b706be2b6bef9980b25cc9cc988dab94bb5.
Fix up build failures in targets I missed in #66003
Kept as 3 commits for reviewers to see better what's changed. Will
squash when
merging.
- reland [InlineAsm] wrap ConstraintCode in enum class NFC (#66003)
- fix all the targets I missed in #66003
- fix off by one found by llvm/test/CodeGen/SystemZ/inline-asm-addr.ll
Added:
Modified:
llvm/include/llvm/CodeGen/SelectionDAGISel.h
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/include/llvm/IR/InlineAsm.h
llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/lib/Target/ARM/ARMISelLowering.h
llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
llvm/lib/Target/AVR/AVRISelLowering.cpp
llvm/lib/Target/AVR/AVRISelLowering.h
llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
llvm/lib/Target/LoongArch/LoongArchISelLowering.h
llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
llvm/lib/Target/M68k/M68kISelLowering.cpp
llvm/lib/Target/M68k/M68kISelLowering.h
llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
llvm/lib/Target/Mips/MipsISelDAGToDAG.h
llvm/lib/Target/Mips/MipsISelLowering.h
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.h
llvm/lib/Target/VE/VEISelDAGToDAG.cpp
llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86ISelLowering.h
llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 557c6ef03d96b98..0179cf8a1f5925c 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -89,9 +89,10 @@ class SelectionDAGISel : public MachineFunctionPass {
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
- virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector<SDValue> &OutOps) {
+ virtual bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
return true;
}
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 12b280d5b1a0bcd..f4feab495932294 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4833,16 +4833,17 @@ class TargetLowering : public TargetLoweringBase {
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const;
- virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
+ virtual InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const {
if (ConstraintCode == "m")
- return InlineAsm::Constraint_m;
+ return InlineAsm::ConstraintCode::m;
if (ConstraintCode == "o")
- return InlineAsm::Constraint_o;
+ return InlineAsm::ConstraintCode::o;
if (ConstraintCode == "X")
- return InlineAsm::Constraint_X;
+ return InlineAsm::ConstraintCode::X;
if (ConstraintCode == "p")
- return InlineAsm::Constraint_p;
- return InlineAsm::Constraint_Unknown;
+ return InlineAsm::ConstraintCode::p;
+ return InlineAsm::ConstraintCode::Unknown;
}
/// Try to replace an X constraint, which matches anything, with another that
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index 8a129337f59266d..36ff7deb6864e2f 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -217,48 +217,6 @@ class InlineAsm final : public Value {
Extra_MayLoad = 8,
Extra_MayStore = 16,
Extra_IsConvergent = 32,
-
- // Memory constraint codes.
- // These could be tablegenerated but there's little need to do that since
- // there's plenty of space in the encoding to support the union of all
- // constraint codes for all targets.
- // Addresses are included here as they need to be treated the same by the
- // backend, the only
diff erence is that they are not used to actaully
- // access memory by the instruction.
- // TODO: convert to enum?
- Constraint_Unknown = 0,
- Constraint_es,
- Constraint_i,
- Constraint_k,
- Constraint_m,
- Constraint_o,
- Constraint_v,
- Constraint_A,
- Constraint_Q,
- Constraint_R,
- Constraint_S,
- Constraint_T,
- Constraint_Um,
- Constraint_Un,
- Constraint_Uq,
- Constraint_Us,
- Constraint_Ut,
- Constraint_Uv,
- Constraint_Uy,
- Constraint_X,
- Constraint_Z,
- Constraint_ZB,
- Constraint_ZC,
- Constraint_Zy,
-
- // Address constraints
- Constraint_p,
- Constraint_ZQ,
- Constraint_ZR,
- Constraint_ZS,
- Constraint_ZT,
-
- Constraints_Max = Constraint_ZT,
};
// Inline asm operands map to multiple SDNode / MachineInstr operands.
@@ -274,6 +232,46 @@ class InlineAsm final : public Value {
Func = 7, // Address operand of function call
};
+ // Memory constraint codes.
+ // Addresses are included here as they need to be treated the same by the
+ // backend, the only
diff erence is that they are not used to actaully
+ // access memory by the instruction.
+ enum class ConstraintCode : uint32_t {
+ Unknown = 0,
+ es,
+ i,
+ k,
+ m,
+ o,
+ v,
+ A,
+ Q,
+ R,
+ S,
+ T,
+ Um,
+ Un,
+ Uq,
+ Us,
+ Ut,
+ Uv,
+ Uy,
+ X,
+ Z,
+ ZB,
+ ZC,
+ Zy,
+
+ // Address constraints
+ p,
+ ZQ,
+ ZR,
+ ZS,
+ ZT,
+
+ Max = ZT,
+ };
+
// These are helper methods for dealing with flags in the INLINEASM SDNode
// in the backend.
//
@@ -375,11 +373,14 @@ class InlineAsm final : public Value {
return true;
}
- // TODO: convert to enum?
- unsigned getMemoryConstraintID() const {
+ ConstraintCode getMemoryConstraintID() const {
assert((isMemKind() || isFuncKind()) &&
"Not expected mem or function flag!");
- return getData();
+ uint32_t D = getData();
+ assert(D <= static_cast<uint32_t>(ConstraintCode::Max) &&
+ D >= static_cast<uint32_t>(ConstraintCode::Unknown) &&
+ "unexpected value for memory constraint");
+ return static_cast<ConstraintCode>(D);
}
/// setMatchingOp - Augment an existing flag with information indicating
@@ -403,12 +404,11 @@ class InlineAsm final : public Value {
/// setMemConstraint - Augment an existing flag with the constraint code for
/// a memory constraint.
- void setMemConstraint(unsigned Constraint) {
+ void setMemConstraint(ConstraintCode C) {
assert((isMemKind() || isFuncKind()) &&
"Flag is not a memory or function constraint!");
- assert(Constraint <= Constraints_Max && "Unknown constraint ID");
assert(getData() == 0 && "Mem constraint already set");
- setData(Constraint);
+ setData(static_cast<uint32_t>(C));
}
/// clearMemConstraint - Similar to setMemConstraint(0), but without the
/// assertion checking that the constraint has not been set previously.
@@ -443,63 +443,63 @@ class InlineAsm final : public Value {
return Result;
}
- static StringRef getMemConstraintName(unsigned Constraint) {
- switch (Constraint) {
- case InlineAsm::Constraint_es:
+ static StringRef getMemConstraintName(ConstraintCode C) {
+ switch (C) {
+ case ConstraintCode::es:
return "es";
- case InlineAsm::Constraint_i:
+ case ConstraintCode::i:
return "i";
- case InlineAsm::Constraint_k:
+ case ConstraintCode::k:
return "k";
- case InlineAsm::Constraint_m:
+ case ConstraintCode::m:
return "m";
- case InlineAsm::Constraint_o:
+ case ConstraintCode::o:
return "o";
- case InlineAsm::Constraint_v:
+ case ConstraintCode::v:
return "v";
- case InlineAsm::Constraint_A:
+ case ConstraintCode::A:
return "A";
- case InlineAsm::Constraint_Q:
+ case ConstraintCode::Q:
return "Q";
- case InlineAsm::Constraint_R:
+ case ConstraintCode::R:
return "R";
- case InlineAsm::Constraint_S:
+ case ConstraintCode::S:
return "S";
- case InlineAsm::Constraint_T:
+ case ConstraintCode::T:
return "T";
- case InlineAsm::Constraint_Um:
+ case ConstraintCode::Um:
return "Um";
- case InlineAsm::Constraint_Un:
+ case ConstraintCode::Un:
return "Un";
- case InlineAsm::Constraint_Uq:
+ case ConstraintCode::Uq:
return "Uq";
- case InlineAsm::Constraint_Us:
+ case ConstraintCode::Us:
return "Us";
- case InlineAsm::Constraint_Ut:
+ case ConstraintCode::Ut:
return "Ut";
- case InlineAsm::Constraint_Uv:
+ case ConstraintCode::Uv:
return "Uv";
- case InlineAsm::Constraint_Uy:
+ case ConstraintCode::Uy:
return "Uy";
- case InlineAsm::Constraint_X:
+ case ConstraintCode::X:
return "X";
- case InlineAsm::Constraint_Z:
+ case ConstraintCode::Z:
return "Z";
- case InlineAsm::Constraint_ZB:
+ case ConstraintCode::ZB:
return "ZB";
- case InlineAsm::Constraint_ZC:
+ case ConstraintCode::ZC:
return "ZC";
- case InlineAsm::Constraint_Zy:
+ case ConstraintCode::Zy:
return "Zy";
- case InlineAsm::Constraint_p:
+ case ConstraintCode::p:
return "p";
- case InlineAsm::Constraint_ZQ:
+ case ConstraintCode::ZQ:
return "ZQ";
- case InlineAsm::Constraint_ZR:
+ case ConstraintCode::ZR:
return "ZR";
- case InlineAsm::Constraint_ZS:
+ case ConstraintCode::ZS:
return "ZS";
- case InlineAsm::Constraint_ZT:
+ case ConstraintCode::ZT:
return "ZT";
default:
llvm_unreachable("Unknown memory constraint");
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index 9944ba15997687a..00dba57fcb80227 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm(
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM instruction to know about this
@@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm(
assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
OpFlags.setMemConstraint(ConstraintID);
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 8cc3391e0d96a3d..d8467e2af8786ec 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 738dd10633db6a5..720fc4944161225 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this output.
@@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
TLI.getPointerTy(DAG.getDataLayout()) &&
"Memory operands expect pointer values");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this input.
@@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
}
if (OpInfo.ConstraintType == TargetLowering::C_Address) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index a7873241df62e52..91b9d77eed70596 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2101,7 +2101,8 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
// Otherwise, this is a memory operand. Ask the target to select it.
std::vector<SDValue> SelOps;
- unsigned ConstraintID = Flags.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode ConstraintID =
+ Flags.getMemoryConstraintID();
if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
report_fatal_error("Could not match memory address. Inline asm"
" failure!");
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 686044ea572ac0d..bf1605f06bd88d6 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment(
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 60a155a86667e89..16ab662ca34aa4f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -62,7 +62,7 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
template <signed Low, signed High, signed Scale>
@@ -533,13 +533,14 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) {
#endif
bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
// We need to make sure that this one operand does not end up in XZR, thus
// require the address to be in a PointerRegClass register.
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 67c344318e0d3ec..f2696b6b97593a1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1169,9 +1169,10 @@ class AArch64TargetLowering : public TargetLowering {
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
- return InlineAsm::Constraint_Q;
+ return InlineAsm::ConstraintCode::Q;
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
// followed by llvm_unreachable so we'll leave them unimplemented in
// the backend for now.
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 5f4fab0675824fd..acd2e4b052b65c9 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -331,7 +331,8 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
// Form pairs of consecutive R, S, D, or Q registers.
@@ -5864,23 +5865,22 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
return true;
}
-
-bool ARMDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector<SDValue> &OutOps) {
+bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
- case InlineAsm::Constraint_Um:
- case InlineAsm::Constraint_Un:
- case InlineAsm::Constraint_Uq:
- case InlineAsm::Constraint_Us:
- case InlineAsm::Constraint_Ut:
- case InlineAsm::Constraint_Uv:
- case InlineAsm::Constraint_Uy:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
+ case InlineAsm::ConstraintCode::Um:
+ case InlineAsm::ConstraintCode::Un:
+ case InlineAsm::ConstraintCode::Uq:
+ case InlineAsm::ConstraintCode::Us:
+ case InlineAsm::ConstraintCode::Ut:
+ case InlineAsm::ConstraintCode::Uv:
+ case InlineAsm::ConstraintCode::Uy:
// Require the address to be in a register. That is safe for all ARM
// variants and it is hard to do anything much smarter without knowing
// how the operand is used.
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 2dd54602ef61b9c..efa82386768605d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -534,29 +534,29 @@ class VectorType;
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
- unsigned
+ InlineAsm::ConstraintCode
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
- return InlineAsm::Constraint_Q;
- else if (ConstraintCode.size() == 2) {
+ return InlineAsm::ConstraintCode::Q;
+ if (ConstraintCode.size() == 2) {
if (ConstraintCode[0] == 'U') {
switch(ConstraintCode[1]) {
default:
break;
case 'm':
- return InlineAsm::Constraint_Um;
+ return InlineAsm::ConstraintCode::Um;
case 'n':
- return InlineAsm::Constraint_Un;
+ return InlineAsm::ConstraintCode::Un;
case 'q':
- return InlineAsm::Constraint_Uq;
+ return InlineAsm::ConstraintCode::Uq;
case 's':
- return InlineAsm::Constraint_Us;
+ return InlineAsm::ConstraintCode::Us;
case 't':
- return InlineAsm::Constraint_Ut;
+ return InlineAsm::ConstraintCode::Ut;
case 'v':
- return InlineAsm::Constraint_Uv;
+ return InlineAsm::ConstraintCode::Uv;
case 'y':
- return InlineAsm::Constraint_Uy;
+ return InlineAsm::ConstraintCode::Uy;
}
}
}
diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
index bbb1de40be63409..214799aa31a9c7f 100644
--- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
@@ -43,7 +43,8 @@ class AVRDAGToDAGISel : public SelectionDAGISel {
bool selectIndexedLoad(SDNode *N);
unsigned selectIndexedProgMemLoad(const LoadSDNode *LD, MVT VT, int Bank);
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ InlineAsm::ConstraintCode ConstraintCode,
std::vector<SDValue> &OutOps) override;
// Include the pieces autogenerated from the target description.
@@ -200,9 +201,10 @@ unsigned AVRDAGToDAGISel::selectIndexedProgMemLoad(const LoadSDNode *LD, MVT VT,
}
bool AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintCode, std::vector<SDValue> &OutOps) {
- assert((ConstraintCode == InlineAsm::Constraint_m ||
- ConstraintCode == InlineAsm::Constraint_Q) &&
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintCode,
+ std::vector<SDValue> &OutOps) {
+ assert((ConstraintCode == InlineAsm::ConstraintCode::m ||
+ ConstraintCode == InlineAsm::ConstraintCode::Q) &&
"Unexpected asm memory constraint");
MachineRegisterInfo &RI = MF->getRegInfo();
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 2b7370409085165..4f5a48bd05a4e86 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -2521,13 +2521,13 @@ AVRTargetLowering::getConstraintType(StringRef Constraint) const {
return TargetLowering::getConstraintType(Constraint);
}
-unsigned
+InlineAsm::ConstraintCode
AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
// Not sure if this is actually the right thing to do, but we got to do
// *something* [agnat]
switch (ConstraintCode[0]) {
case 'Q':
- return InlineAsm::Constraint_Q;
+ return InlineAsm::ConstraintCode::Q;
}
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
}
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.h b/llvm/lib/Target/AVR/AVRISelLowering.h
index b696bebe7136f42..6815b519bebf74d 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.h
+++ b/llvm/lib/Target/AVR/AVRISelLowering.h
@@ -133,7 +133,8 @@ class AVRTargetLowering : public TargetLowering {
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
std::vector<SDValue> &Ops,
diff --git a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
index 6cfeb9eab46e87e..b0cfca3b7ab66a7 100644
--- a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
+++ b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
@@ -61,10 +61,10 @@ class BPFDAGToDAGISel : public SelectionDAGISel {
void PreprocessISelDAG() override;
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ InlineAsm::ConstraintCode ConstraintCode,
std::vector<SDValue> &OutOps) override;
-
private:
// Include the pieces autogenerated from the target description.
#include "BPFGenDAGISel.inc"
@@ -159,12 +159,13 @@ bool BPFDAGToDAGISel::SelectFIAddr(SDValue Addr, SDValue &Base,
}
bool BPFDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintCode, std::vector<SDValue> &OutOps) {
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintCode,
+ std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintCode) {
default:
return true;
- case InlineAsm::Constraint_m: // memory
+ case InlineAsm::ConstraintCode::m: // memory
if (!SelectAddr(Op, Op0, Op1))
return true;
break;
diff --git a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
index 32fa4ea1e302b68..1a3c9f14c1d5a8b 100644
--- a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
@@ -48,7 +48,8 @@ class CSKYDAGToDAGISel : public SelectionDAGISel {
SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
#include "CSKYGenDAGISel.inc"
@@ -383,9 +384,10 @@ SDNode *CSKYDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
}
bool CSKYDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
switch (ConstraintID) {
- case InlineAsm::Constraint_m:
+ case InlineAsm::ConstraintCode::m:
// We just support simple memory operands that have a single address
// operand and need no special handling.
OutOps.push_back(Op);
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index e1db9f1f04f4dce..4c340a42748e116 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -955,17 +955,17 @@ void HexagonDAGToDAGISel::Select(SDNode *N) {
SelectCode(N);
}
-bool HexagonDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector<SDValue> &OutOps) {
+bool HexagonDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
SDValue Inp = Op, Res;
switch (ConstraintID) {
default:
return true;
- case InlineAsm::Constraint_o: // Offsetable.
- case InlineAsm::Constraint_v: // Not offsetable.
- case InlineAsm::Constraint_m: // Memory.
+ case InlineAsm::ConstraintCode::o: // Offsetable.
+ case InlineAsm::ConstraintCode::v: // Not offsetable.
+ case InlineAsm::ConstraintCode::m: // Memory.
if (SelectAddrFI(Inp, Res))
OutOps.push_back(Res);
else
@@ -977,7 +977,6 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
return false;
}
-
static bool isMemOPCandidate(SDNode *I, SDNode *U) {
// I is an operand of U. Check if U is an arithmetic (binary) operation
// usable in a memop, where the other operand is a loaded value, and the
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
index 061da2a69ba4f87..bc650571d2a51a8 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
@@ -85,7 +85,7 @@ class HexagonDAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
bool tryLoadOfLoadIntrinsic(LoadSDNode *N);
bool SelectBrevLdIntrinsic(SDNode *IntN);
diff --git a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
index e0d73587ec1babb..6f5495ac00e1575 100644
--- a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
@@ -59,7 +59,8 @@ class LanaiDAGToDAGISel : public SelectionDAGISel {
return SelectionDAGISel::runOnMachineFunction(MF);
}
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ InlineAsm::ConstraintCode ConstraintCode,
std::vector<SDValue> &OutOps) override;
private:
@@ -284,12 +285,13 @@ bool LanaiDAGToDAGISel::selectAddrRr(SDValue Addr, SDValue &R1, SDValue &R2,
}
bool LanaiDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintCode, std::vector<SDValue> &OutOps) {
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintCode,
+ std::vector<SDValue> &OutOps) {
SDValue Op0, Op1, AluOp;
switch (ConstraintCode) {
default:
return true;
- case InlineAsm::Constraint_m: // memory
+ case InlineAsm::ConstraintCode::m: // memory
if (!selectAddrRr(Op, Op0, Op1, AluOp) &&
!selectAddrRi(Op, Op0, Op1, AluOp))
return true;
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
index f55184019988ebb..0cfee6025218884 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
@@ -91,7 +91,8 @@ void LoongArchDAGToDAGISel::Select(SDNode *Node) {
}
bool LoongArchDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
SDValue Base = Op;
SDValue Offset =
CurDAG->getTargetConstant(0, SDLoc(Op), Subtarget->getGRLenVT());
@@ -99,12 +100,12 @@ bool LoongArchDAGToDAGISel::SelectInlineAsmMemoryOperand(
default:
llvm_unreachable("unexpected asm memory constraint");
// Reg+Reg addressing.
- case InlineAsm::Constraint_k:
+ case InlineAsm::ConstraintCode::k:
Base = Op.getOperand(0);
Offset = Op.getOperand(1);
break;
// Reg+simm12 addressing.
- case InlineAsm::Constraint_m:
+ case InlineAsm::ConstraintCode::m:
if (CurDAG->isBaseWithConstantOffset(Op)) {
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op.getOperand(1));
if (isIntN(12, CN->getSExtValue())) {
@@ -115,10 +116,10 @@ bool LoongArchDAGToDAGISel::SelectInlineAsmMemoryOperand(
}
break;
// Reg+0 addressing.
- case InlineAsm::Constraint_ZB:
+ case InlineAsm::ConstraintCode::ZB:
break;
// Reg+(simm14<<2) addressing.
- case InlineAsm::Constraint_ZC:
+ case InlineAsm::ConstraintCode::ZC:
if (CurDAG->isBaseWithConstantOffset(Op)) {
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op.getOperand(1));
if (isIntN(16, CN->getSExtValue()) &&
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
index 5e3d6ccc3755c06..48a178bfeb95f95 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
@@ -38,7 +38,8 @@ class LoongArchDAGToDAGISel : public SelectionDAGISel {
void Select(SDNode *Node) override;
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
bool SelectBaseAddr(SDValue Addr, SDValue &Base);
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 2f8ce57d3f5f5b9..c74093b3f14e242 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -4296,12 +4296,12 @@ LoongArchTargetLowering::getConstraintType(StringRef Constraint) const {
return TargetLowering::getConstraintType(Constraint);
}
-unsigned LoongArchTargetLowering::getInlineAsmMemConstraint(
+InlineAsm::ConstraintCode LoongArchTargetLowering::getInlineAsmMemConstraint(
StringRef ConstraintCode) const {
- return StringSwitch<unsigned>(ConstraintCode)
- .Case("k", InlineAsm::Constraint_k)
- .Case("ZB", InlineAsm::Constraint_ZB)
- .Case("ZC", InlineAsm::Constraint_ZC)
+ return StringSwitch<InlineAsm::ConstraintCode>(ConstraintCode)
+ .Case("k", InlineAsm::ConstraintCode::k)
+ .Case("ZB", InlineAsm::ConstraintCode::ZB)
+ .Case("ZC", InlineAsm::ConstraintCode::ZC)
.Default(TargetLowering::getInlineAsmMemConstraint(ConstraintCode));
}
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index 7765057ebffb424..9d531894a13786c 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -283,7 +283,8 @@ class LoongArchTargetLowering : public TargetLowering {
ConstraintType getConstraintType(StringRef Constraint) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
index e33654ea3f18665..c400c9a3fc992f9 100644
--- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
+++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
@@ -227,7 +227,8 @@ class M68kDAGToDAGISel : public SelectionDAGISel {
bool SelectPCD(SDNode *Parent, SDValue N, SDValue &Imm);
bool SelectPCI(SDNode *Parent, SDValue N, SDValue &Imm, SDValue &Index);
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
// If Address Mode represents Frame Index store FI in Disp and
@@ -953,7 +954,8 @@ bool M68kDAGToDAGISel::SelectARI(SDNode *Parent, SDValue N, SDValue &Base) {
}
bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
// In order to tell AsmPrinter the exact addressing mode we select here, which
// might comprise of multiple SDValues (hence MachineOperands), a 32-bit
// immediate value is prepended to the list of selected SDValues to indicate
@@ -966,7 +968,7 @@ bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand(
switch (ConstraintID) {
// Generic memory operand.
- case InlineAsm::Constraint_m: {
+ case InlineAsm::ConstraintCode::m: {
// Try every supported (memory) addressing modes.
SDValue Operands[4];
@@ -997,7 +999,7 @@ bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand(
return true;
}
// 'Q': Address register indirect addressing.
- case InlineAsm::Constraint_Q: {
+ case InlineAsm::ConstraintCode::Q: {
SDValue AMKind, Base;
// 'j' addressing mode.
// TODO: Add support for 'o' and 'e' after their
@@ -1009,7 +1011,7 @@ bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand(
return true;
}
// 'U': Address register indirect w/ constant offset addressing.
- case InlineAsm::Constraint_Um: {
+ case InlineAsm::ConstraintCode::Um: {
SDValue AMKind, Base, Offset;
// 'p' addressing mode.
if (SelectARID(nullptr, Op, Offset, Base) && addKind(AMKind, AMK::p)) {
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
index ae3c348a59999e1..82f6d7323cf60b4 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -204,11 +204,12 @@ M68kTargetLowering::getExceptionSelectorRegister(const Constant *) const {
return M68k::D1;
}
-unsigned
+InlineAsm::ConstraintCode
M68kTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
- return StringSwitch<unsigned>(ConstraintCode)
- .Case("Q", InlineAsm::Constraint_Q)
- .Case("U", InlineAsm::Constraint_Um) // We borrow Constraint_Um for 'U'.
+ return StringSwitch<InlineAsm::ConstraintCode>(ConstraintCode)
+ .Case("Q", InlineAsm::ConstraintCode::Q)
+ // We borrow ConstraintCode::Um for 'U'.
+ .Case("U", InlineAsm::ConstraintCode::Um)
.Default(TargetLowering::getInlineAsmMemConstraint(ConstraintCode));
}
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.h b/llvm/lib/Target/M68k/M68kISelLowering.h
index 5f279b3dcbd3ee4..37e66695fde9036 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.h
+++ b/llvm/lib/Target/M68k/M68kISelLowering.h
@@ -187,7 +187,8 @@ class M68kTargetLowering : public TargetLowering {
Register
getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
private:
unsigned GetAlignedArgumentStackSize(unsigned StackSize,
diff --git a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
index 88f072c78036719..cb5d97914725632 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
@@ -103,7 +103,8 @@ namespace {
bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
// Include the pieces autogenerated from the target description.
@@ -282,13 +283,13 @@ bool MSP430DAGToDAGISel::SelectAddr(SDValue N,
return true;
}
-bool MSP430DAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector<SDValue> &OutOps) {
+bool MSP430DAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintID) {
default: return true;
- case InlineAsm::Constraint_m: // memory
+ case InlineAsm::ConstraintCode::m: // memory
if (!SelectAddr(Op, Op0, Op1))
return true;
break;
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
index 7266dfb206a8a28..77ce8ba890a814c 100644
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -308,16 +308,16 @@ void MipsDAGToDAGISel::Select(SDNode *Node) {
SelectCode(Node);
}
-bool MipsDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector<SDValue> &OutOps) {
+bool MipsDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
// All memory constraints can at least accept raw pointers.
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_R:
- case InlineAsm::Constraint_ZC:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::R:
+ case InlineAsm::ConstraintCode::ZC:
OutOps.push_back(Op);
return false;
}
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
index d13efdaab2b6991..9c861017ec72a53 100644
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
@@ -141,7 +141,7 @@ class MipsDAGToDAGISel : public SelectionDAGISel {
virtual void processFunctionAfterISel(MachineFunction &MF) = 0;
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
};
}
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h
index 8614c4d3abe5a2b..4b5700b7e28dd27 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.h
+++ b/llvm/lib/Target/Mips/MipsISelLowering.h
@@ -646,14 +646,14 @@ class TargetRegisterClass;
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
- unsigned
+ InlineAsm::ConstraintCode
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "o")
- return InlineAsm::Constraint_o;
+ return InlineAsm::ConstraintCode::o;
if (ConstraintCode == "R")
- return InlineAsm::Constraint_R;
+ return InlineAsm::ConstraintCode::R;
if (ConstraintCode == "ZC")
- return InlineAsm::Constraint_ZC;
+ return InlineAsm::ConstraintCode::ZC;
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
}
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
index 138735d44df6dc4..0bb16f3111efb15 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -1377,17 +1377,17 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
return false;
}
-bool MipsSEDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector<SDValue> &OutOps) {
+bool MipsSEDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
SDValue Base, Offset;
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
// All memory constraints can at least accept raw pointers.
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
if (selectAddrRegImm16(Op, Base, Offset)) {
OutOps.push_back(Base);
OutOps.push_back(Offset);
@@ -1396,7 +1396,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
OutOps.push_back(Op);
OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
return false;
- case InlineAsm::Constraint_R:
+ case InlineAsm::ConstraintCode::R:
// The 'R' constraint is supposed to be much more complicated than this.
// However, it's becoming less useful due to architectural changes and
// ought to be replaced by other constraints such as 'ZC'.
@@ -1410,7 +1410,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
OutOps.push_back(Op);
OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
return false;
- case InlineAsm::Constraint_ZC:
+ case InlineAsm::ConstraintCode::ZC:
// ZC matches whatever the pref, ll, and sc instructions can handle for the
// given subtarget.
if (Subtarget->inMicroMipsMode()) {
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
index 39f665be571e38d..f3b887286db8288 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
@@ -135,7 +135,7 @@ class MipsSEDAGToDAGISel : public MipsDAGToDAGISel {
void processFunctionAfterISel(MachineFunction &MF) override;
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
};
diff --git a/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp b/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
index 2683d92c1f2eac9..61471050c08fab5 100644
--- a/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
@@ -103,7 +103,7 @@ static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode,
case Mips::INLINEASM: {
const InlineAsm::Flag F(MO.getImm());
switch (F.getMemoryConstraintID()) {
- case InlineAsm::Constraint_ZC: {
+ case InlineAsm::ConstraintCode::ZC: {
const MipsSubtarget &Subtarget = MO.getParent()
->getParent()
->getParent()
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index 4f3ee26990cefcd..62991df958daa4c 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -3581,12 +3581,13 @@ bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N,
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintID) {
default:
return true;
- case InlineAsm::Constraint_m: // memory
+ case InlineAsm::ConstraintCode::m: // memory
if (SelectDirectAddr(Op, Op0)) {
OutOps.push_back(Op0);
OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
index 25bb73cd5536121..b283dc9be068e99 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
@@ -13,12 +13,13 @@
#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELDAGTODAG_H
#define LLVM_LIB_TARGET_NVPTX_NVPTXISELDAGTODAG_H
+#include "MCTargetDesc/NVPTXBaseInfo.h"
#include "NVPTX.h"
#include "NVPTXISelLowering.h"
#include "NVPTXRegisterInfo.h"
#include "NVPTXTargetMachine.h"
-#include "MCTargetDesc/NVPTXBaseInfo.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/Support/Compiler.h"
@@ -49,8 +50,9 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
const NVPTXSubtarget *Subtarget = nullptr;
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
+
private:
// Include the pieces autogenerated from the target description.
#include "NVPTXGenDAGISel.inc"
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 61a3138007db900..1c2f562a0b3b6c6 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -387,18 +387,19 @@ namespace {
/// register can be improved, but it is wrong to substitute Reg+Reg for
/// Reg in an asm, because the load or store opcode would have to change.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override {
switch(ConstraintID) {
default:
- errs() << "ConstraintID: " << ConstraintID << "\n";
+ errs() << "ConstraintID: "
+ << InlineAsm::getMemConstraintName(ConstraintID) << "\n";
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_es:
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
- case InlineAsm::Constraint_Z:
- case InlineAsm::Constraint_Zy:
+ case InlineAsm::ConstraintCode::es:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
+ case InlineAsm::ConstraintCode::Z:
+ case InlineAsm::ConstraintCode::Zy:
// We need to make sure that this one operand does not end up in r0
// (because we might end up lowering this as 0(%op)).
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 8cbefbdb917359e..7c62e370f1536a4 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -980,16 +980,16 @@ namespace llvm {
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
- unsigned
+ InlineAsm::ConstraintCode
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "es")
- return InlineAsm::Constraint_es;
+ return InlineAsm::ConstraintCode::es;
else if (ConstraintCode == "Q")
- return InlineAsm::Constraint_Q;
+ return InlineAsm::ConstraintCode::Q;
else if (ConstraintCode == "Z")
- return InlineAsm::Constraint_Z;
+ return InlineAsm::ConstraintCode::Z;
else if (ConstraintCode == "Zy")
- return InlineAsm::Constraint_Zy;
+ return InlineAsm::ConstraintCode::Zy;
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index c6cefc000b3f746..d5c1ab4718dbdf4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2163,12 +2163,13 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
}
bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
// Always produce a register and immediate operand, as expected by
// RISCVAsmPrinter::PrintAsmMemoryOperand.
switch (ConstraintID) {
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_m: {
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::m: {
SDValue Op0, Op1;
bool Found = SelectAddrRegImm(Op, Op0, Op1);
assert(Found && "SelectAddrRegImm should always succeed");
@@ -2177,7 +2178,7 @@ bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
OutOps.push_back(Op1);
return false;
}
- case InlineAsm::Constraint_A:
+ case InlineAsm::ConstraintCode::A:
OutOps.push_back(Op);
OutOps.push_back(
CurDAG->getTargetConstant(0, SDLoc(Op), Subtarget->getXLenVT()));
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index fbc1520a54ba071..b9117a4c5efeaa4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -43,7 +43,8 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
void Select(SDNode *Node) override;
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a470ceae90ce591..a89961dccc70f3d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17418,13 +17418,13 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
return Res;
}
-unsigned
+InlineAsm::ConstraintCode
RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
// Currently only support length 1 constraints.
if (ConstraintCode.size() == 1) {
switch (ConstraintCode[0]) {
case 'A':
- return InlineAsm::Constraint_A;
+ return InlineAsm::ConstraintCode::A;
default:
break;
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 461b929643f2688..e4481a0f6752fa3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -566,7 +566,8 @@ class RISCVTargetLowering : public TargetLowering {
ConstraintType getConstraintType(StringRef Constraint) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 8df63d8d23147dd..3c9841d81b4f3f3 100644
--- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -56,7 +56,7 @@ class SparcDAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
// Include the pieces autogenerated from the target description.
@@ -375,18 +375,17 @@ void SparcDAGToDAGISel::Select(SDNode *N) {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
-bool
-SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector<SDValue> &OutOps) {
+bool SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintID) {
default: return true;
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_m: // memory
- if (!SelectADDRrr(Op, Op0, Op1))
- SelectADDRri(Op, Op0, Op1);
- break;
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::m: // memory
+ if (!SelectADDRrr(Op, Op0, Op1))
+ SelectADDRri(Op, Op0, Op1);
+ break;
}
OutOps.push_back(Op0);
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index 1e9e2917a3aa663..f88e365d3f52874 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -368,7 +368,8 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
// Override SelectionDAGISel.
void Select(SDNode *Node) override;
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
void PreprocessISelDAG() override;
@@ -1677,10 +1678,9 @@ void SystemZDAGToDAGISel::Select(SDNode *Node) {
SelectCode(Node);
}
-bool SystemZDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector<SDValue> &OutOps) {
+bool SystemZDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
SystemZAddressingMode::AddrForm Form;
SystemZAddressingMode::DispRange DispRange;
SDValue Base, Disp, Index;
@@ -1688,30 +1688,30 @@ SelectInlineAsmMemoryOperand(const SDValue &Op,
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_i:
- case InlineAsm::Constraint_Q:
- case InlineAsm::Constraint_ZQ:
+ case InlineAsm::ConstraintCode::i:
+ case InlineAsm::ConstraintCode::Q:
+ case InlineAsm::ConstraintCode::ZQ:
// Accept an address with a short displacement, but no index.
Form = SystemZAddressingMode::FormBD;
DispRange = SystemZAddressingMode::Disp12Only;
break;
- case InlineAsm::Constraint_R:
- case InlineAsm::Constraint_ZR:
+ case InlineAsm::ConstraintCode::R:
+ case InlineAsm::ConstraintCode::ZR:
// Accept an address with a short displacement and an index.
Form = SystemZAddressingMode::FormBDXNormal;
DispRange = SystemZAddressingMode::Disp12Only;
break;
- case InlineAsm::Constraint_S:
- case InlineAsm::Constraint_ZS:
+ case InlineAsm::ConstraintCode::S:
+ case InlineAsm::ConstraintCode::ZS:
// Accept an address with a long displacement, but no index.
Form = SystemZAddressingMode::FormBD;
DispRange = SystemZAddressingMode::Disp20Only;
break;
- case InlineAsm::Constraint_T:
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_p:
- case InlineAsm::Constraint_ZT:
+ case InlineAsm::ConstraintCode::T:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::p:
+ case InlineAsm::ConstraintCode::ZT:
// Accept an address with a long displacement and an index.
// m works the same as T, as this is the most general case.
// We don't really have any special handling of "offsettable"
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index 47fa1831c3ee7f5..8feeb61abd79856 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -492,34 +492,35 @@ class SystemZTargetLowering : public TargetLowering {
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode.size() == 1) {
switch(ConstraintCode[0]) {
default:
break;
case 'o':
- return InlineAsm::Constraint_o;
+ return InlineAsm::ConstraintCode::o;
case 'Q':
- return InlineAsm::Constraint_Q;
+ return InlineAsm::ConstraintCode::Q;
case 'R':
- return InlineAsm::Constraint_R;
+ return InlineAsm::ConstraintCode::R;
case 'S':
- return InlineAsm::Constraint_S;
+ return InlineAsm::ConstraintCode::S;
case 'T':
- return InlineAsm::Constraint_T;
+ return InlineAsm::ConstraintCode::T;
}
} else if (ConstraintCode.size() == 2 && ConstraintCode[0] == 'Z') {
switch (ConstraintCode[1]) {
default:
break;
case 'Q':
- return InlineAsm::Constraint_ZQ;
+ return InlineAsm::ConstraintCode::ZQ;
case 'R':
- return InlineAsm::Constraint_ZR;
+ return InlineAsm::ConstraintCode::ZR;
case 'S':
- return InlineAsm::Constraint_ZS;
+ return InlineAsm::ConstraintCode::ZS;
case 'T':
- return InlineAsm::Constraint_ZT;
+ return InlineAsm::ConstraintCode::ZT;
}
}
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
diff --git a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
index 859c33df40284df..87646bc1a12ff25 100644
--- a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
@@ -58,7 +58,7 @@ class VEDAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
// Include the pieces autogenerated from the target description.
@@ -301,16 +301,15 @@ void VEDAGToDAGISel::Select(SDNode *N) {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
-bool
-VEDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector<SDValue> &OutOps) {
+bool VEDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_m: // memory
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::m: // memory
// Try to match ADDRri since reg+imm style is safe for all VE instructions
// with a memory operand.
if (selectADDRri(Op, Op0, Op1)) {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
index 9aacddb0187eb88..3d1022de85b5305 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
@@ -64,7 +64,8 @@ class WebAssemblyDAGToDAGISel final : public SelectionDAGISel {
void Select(SDNode *Node) override;
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
bool SelectAddrOperands32(SDValue Op, SDValue &Offset, SDValue &Addr);
@@ -293,9 +294,10 @@ void WebAssemblyDAGToDAGISel::Select(SDNode *Node) {
}
bool WebAssemblyDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
switch (ConstraintID) {
- case InlineAsm::Constraint_m:
+ case InlineAsm::ConstraintCode::m:
// We just support simple memory operands that just have a single address
// operand and need no special handling.
OutOps.push_back(Op);
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 5ebb0a8239aa38b..fed26111f60ec65 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -259,7 +259,7 @@ namespace {
/// Implement addressing mode selection for inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
void emitSpecialCodeForMain();
@@ -6323,18 +6323,18 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
SelectCode(Node);
}
-bool X86DAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector<SDValue> &OutOps) {
+bool X86DAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
SDValue Op0, Op1, Op2, Op3, Op4;
switch (ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_o: // offsetable ??
- case InlineAsm::Constraint_v: // not offsetable ??
- case InlineAsm::Constraint_m: // memory
- case InlineAsm::Constraint_X:
- case InlineAsm::Constraint_p: // address
+ case InlineAsm::ConstraintCode::o: // offsetable ??
+ case InlineAsm::ConstraintCode::v: // not offsetable ??
+ case InlineAsm::ConstraintCode::m: // memory
+ case InlineAsm::ConstraintCode::X:
+ case InlineAsm::ConstraintCode::p: // address
if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
return true;
break;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 5689543fcd1fa2c..4d45a0a58442105 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -1279,10 +1279,10 @@ namespace llvm {
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
- unsigned
+ InlineAsm::ConstraintCode
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "v")
- return InlineAsm::Constraint_v;
+ return InlineAsm::ConstraintCode::v;
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
}
diff --git a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
index 949b88ad8d4e2f3..54ee759b1ef3daf 100644
--- a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
@@ -71,7 +71,8 @@ namespace {
// Complex Pattern Selectors.
bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset);
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
// Include the pieces autogenerated from the target description.
@@ -114,13 +115,13 @@ bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base,
return false;
}
-bool XCoreDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector<SDValue> &OutOps) {
+bool XCoreDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
SDValue Reg;
switch (ConstraintID) {
default: return true;
- case InlineAsm::Constraint_m: // Memory.
+ case InlineAsm::ConstraintCode::m: // Memory.
switch (Op.getOpcode()) {
default: return true;
case XCoreISD::CPRelativeWrapper:
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