[llvm] 8d99bf9 - [JITLink][AArch32] Revisit descriptions for Call and Jump24 relocation types (NFC)

[Stefan Gränitz via llvm-commits]

Author: Stefan Gränitz
Date: 2023-09-13T18:59:08+02:00
New Revision: 8d99bf92b5521ae2bba33a9920f7647968e023ec

URL: https://github.com/llvm/llvm-project/commit/8d99bf92b5521ae2bba33a9920f7647968e023ec
DIFF: https://github.com/llvm/llvm-project/commit/8d99bf92b5521ae2bba33a9920f7647968e023ec.diff

LOG: [JITLink][AArch32] Revisit descriptions for Call and Jump24 relocation types (NFC)

Added: 
    

Modified: 
    llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
    llvm/unittests/ExecutionEngine/JITLink/AArch32Tests.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h b/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
index 1c89280a10fd213..05391baecb9a59b 100644
--- a/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
+++ b/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
@@ -48,11 +48,15 @@ enum EdgeKind_aarch32 : Edge::Kind {
   ///
   FirstArmRelocation,
 
-  /// Write immediate value for PC-relative branch with link (can bridge between
-  /// Arm and Thumb).
+  /// Write immediate value for unconditional PC-relative branch with link.
+  /// We patch the instruction opcode to account for an instruction-set state
+  /// switch: we use the bl instruction to stay in ARM and the blx instruction
+  /// to switch to Thumb.
   Arm_Call = FirstArmRelocation,
 
-  /// Write immediate value for (unconditional) PC-relative branch without link.
+  /// Write immediate value for conditional PC-relative branch without link.
+  /// If the branch target is not ARM, we are forced to generate an explicit
+  /// interworking stub.
   Arm_Jump24,
 
   LastArmRelocation = Arm_Jump24,
@@ -62,11 +66,15 @@ enum EdgeKind_aarch32 : Edge::Kind {
   ///
   FirstThumbRelocation,
 
-  /// Write immediate value for PC-relative branch with link (can bridge between
-  /// Arm and Thumb).
+  /// Write immediate value for unconditional PC-relative branch with link.
+  /// We patch the instruction opcode to account for an instruction-set state
+  /// switch: we use the bl instruction to stay in Thumb and the blx instruction
+  /// to switch to ARM.
   Thumb_Call = FirstThumbRelocation,
 
-  /// Write immediate value for (unconditional) PC-relative branch without link.
+  /// Write immediate value for PC-relative branch without link. The instruction
+  /// can be made conditional by an IT block. If the branch target is not ARM,
+  /// we are forced to generate an explicit interworking stub.
   Thumb_Jump24,
 
   /// Write immediate value to the lower halfword of the destination register

diff  --git a/llvm/unittests/ExecutionEngine/JITLink/AArch32Tests.cpp b/llvm/unittests/ExecutionEngine/JITLink/AArch32Tests.cpp
index 2f9e44daea7a1db..15c00baebe8ce54 100644
--- a/llvm/unittests/ExecutionEngine/JITLink/AArch32Tests.cpp
+++ b/llvm/unittests/ExecutionEngine/JITLink/AArch32Tests.cpp
@@ -234,7 +234,7 @@ TEST(AArch32_Relocations, Thumb_MovtAbs) {
       EXPECT_EQ(EncodeDecode(0xffff, Mem), 0xffff);   // Maximum value
       EXPECT_NE(EncodeDecode(0x10000, Mem), 0x10000); // First overflow
 
-      // Destination register as well as unaffacted bits should be intact
+      // Destination register as well as unaffected bits should be intact
       EXPECT_EQ(decodeRegMovtT1MovwT3(Mem.Hi, Mem.Lo), Reg);
       EXPECT_TRUE(UnaffectedBits.Hi == (Mem.Hi & ~(ImmMask.Hi | RegMask.Hi)) &&
                   UnaffectedBits.Lo == (Mem.Lo & ~(ImmMask.Lo | RegMask.Lo)))