[llvm] ee643b7 - Revert "[InlineAsm] wrap ConstraintCode in enum class NFC (#66003)"
Reid Kleckner via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 13 09:58:14 PDT 2023
Author: Reid Kleckner
Date: 2023-09-13T09:58:02-07:00
New Revision: ee643b706be2b6bef9980b25cc9cc988dab94bb5
URL: https://github.com/llvm/llvm-project/commit/ee643b706be2b6bef9980b25cc9cc988dab94bb5
DIFF: https://github.com/llvm/llvm-project/commit/ee643b706be2b6bef9980b25cc9cc988dab94bb5.diff
LOG: Revert "[InlineAsm] wrap ConstraintCode in enum class NFC (#66003)"
This reverts commit 2ca4d136124d151216aac77a0403dcb5c5835bcd.
Also revert the followup, "[InlineAsm] fix botched merge conflict resolution"
This reverts commit 8b9bf3a9f715ee5dce96eb1194441850c3663da1.
There were SystemZ and Mips build errors, too many to fix forward.
Added:
Modified:
llvm/include/llvm/CodeGen/SelectionDAGISel.h
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/include/llvm/IR/InlineAsm.h
llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/lib/Target/ARM/ARMISelLowering.h
llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
llvm/lib/Target/AVR/AVRISelLowering.cpp
llvm/lib/Target/AVR/AVRISelLowering.h
llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
llvm/lib/Target/M68k/M68kISelLowering.cpp
llvm/lib/Target/M68k/M68kISelLowering.h
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86ISelLowering.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 0179cf8a1f5925c..557c6ef03d96b98 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -89,10 +89,9 @@ class SelectionDAGISel : public MachineFunctionPass {
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
- virtual bool
- SelectInlineAsmMemoryOperand(const SDValue &Op,
- InlineAsm::ConstraintCode ConstraintID,
- std::vector<SDValue> &OutOps) {
+ virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ unsigned ConstraintID,
+ std::vector<SDValue> &OutOps) {
return true;
}
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index f4feab495932294..12b280d5b1a0bcd 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4833,17 +4833,16 @@ class TargetLowering : public TargetLoweringBase {
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const;
- virtual InlineAsm::ConstraintCode
- getInlineAsmMemConstraint(StringRef ConstraintCode) const {
+ virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
if (ConstraintCode == "m")
- return InlineAsm::ConstraintCode::m;
+ return InlineAsm::Constraint_m;
if (ConstraintCode == "o")
- return InlineAsm::ConstraintCode::o;
+ return InlineAsm::Constraint_o;
if (ConstraintCode == "X")
- return InlineAsm::ConstraintCode::X;
+ return InlineAsm::Constraint_X;
if (ConstraintCode == "p")
- return InlineAsm::ConstraintCode::p;
- return InlineAsm::ConstraintCode::Unknown;
+ return InlineAsm::Constraint_p;
+ return InlineAsm::Constraint_Unknown;
}
/// Try to replace an X constraint, which matches anything, with another that
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index 224aef31807a454..8a129337f59266d 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -217,6 +217,48 @@ class InlineAsm final : public Value {
Extra_MayLoad = 8,
Extra_MayStore = 16,
Extra_IsConvergent = 32,
+
+ // Memory constraint codes.
+ // These could be tablegenerated but there's little need to do that since
+ // there's plenty of space in the encoding to support the union of all
+ // constraint codes for all targets.
+ // Addresses are included here as they need to be treated the same by the
+ // backend, the only
diff erence is that they are not used to actaully
+ // access memory by the instruction.
+ // TODO: convert to enum?
+ Constraint_Unknown = 0,
+ Constraint_es,
+ Constraint_i,
+ Constraint_k,
+ Constraint_m,
+ Constraint_o,
+ Constraint_v,
+ Constraint_A,
+ Constraint_Q,
+ Constraint_R,
+ Constraint_S,
+ Constraint_T,
+ Constraint_Um,
+ Constraint_Un,
+ Constraint_Uq,
+ Constraint_Us,
+ Constraint_Ut,
+ Constraint_Uv,
+ Constraint_Uy,
+ Constraint_X,
+ Constraint_Z,
+ Constraint_ZB,
+ Constraint_ZC,
+ Constraint_Zy,
+
+ // Address constraints
+ Constraint_p,
+ Constraint_ZQ,
+ Constraint_ZR,
+ Constraint_ZS,
+ Constraint_ZT,
+
+ Constraints_Max = Constraint_ZT,
};
// Inline asm operands map to multiple SDNode / MachineInstr operands.
@@ -232,46 +274,6 @@ class InlineAsm final : public Value {
Func = 7, // Address operand of function call
};
- // Memory constraint codes.
- // Addresses are included here as they need to be treated the same by the
- // backend, the only
diff erence is that they are not used to actaully
- // access memory by the instruction.
- enum class ConstraintCode : uint32_t {
- Unknown = 0,
- es,
- i,
- k,
- m,
- o,
- v,
- A,
- Q,
- R,
- S,
- T,
- Um,
- Un,
- Uq,
- Us,
- Ut,
- Uv,
- Uy,
- X,
- Z,
- ZB,
- ZC,
- Zy,
-
- // Address constraints
- p,
- ZQ,
- ZR,
- ZS,
- ZT,
-
- Max = ZT,
- };
-
// These are helper methods for dealing with flags in the INLINEASM SDNode
// in the backend.
//
@@ -373,14 +375,11 @@ class InlineAsm final : public Value {
return true;
}
- ConstraintCode getMemoryConstraintID() const {
+ // TODO: convert to enum?
+ unsigned getMemoryConstraintID() const {
assert((isMemKind() || isFuncKind()) &&
"Not expected mem or function flag!");
- uint32_t D = getData();
- assert(D < static_cast<uint32_t>(ConstraintCode::Max) &&
- D >= static_cast<uint32_t>(ConstraintCode::Unknown) &&
- "unexpected value for memory constraint");
- return static_cast<ConstraintCode>(D);
+ return getData();
}
/// setMatchingOp - Augment an existing flag with information indicating
@@ -404,11 +403,12 @@ class InlineAsm final : public Value {
/// setMemConstraint - Augment an existing flag with the constraint code for
/// a memory constraint.
- void setMemConstraint(ConstraintCode C) {
+ void setMemConstraint(unsigned Constraint) {
assert((isMemKind() || isFuncKind()) &&
"Flag is not a memory or function constraint!");
+ assert(Constraint <= Constraints_Max && "Unknown constraint ID");
assert(getData() == 0 && "Mem constraint already set");
- setData(static_cast<uint32_t>(C));
+ setData(Constraint);
}
/// clearMemConstraint - Similar to setMemConstraint(0), but without the
/// assertion checking that the constraint has not been set previously.
@@ -443,63 +443,63 @@ class InlineAsm final : public Value {
return Result;
}
- static StringRef getMemConstraintName(ConstraintCode C) {
- switch (C) {
- case ConstraintCode::es:
+ static StringRef getMemConstraintName(unsigned Constraint) {
+ switch (Constraint) {
+ case InlineAsm::Constraint_es:
return "es";
- case ConstraintCode::i:
+ case InlineAsm::Constraint_i:
return "i";
- case ConstraintCode::k:
+ case InlineAsm::Constraint_k:
return "k";
- case ConstraintCode::m:
+ case InlineAsm::Constraint_m:
return "m";
- case ConstraintCode::o:
+ case InlineAsm::Constraint_o:
return "o";
- case ConstraintCode::v:
+ case InlineAsm::Constraint_v:
return "v";
- case ConstraintCode::A:
+ case InlineAsm::Constraint_A:
return "A";
- case ConstraintCode::Q:
+ case InlineAsm::Constraint_Q:
return "Q";
- case ConstraintCode::R:
+ case InlineAsm::Constraint_R:
return "R";
- case ConstraintCode::S:
+ case InlineAsm::Constraint_S:
return "S";
- case ConstraintCode::T:
+ case InlineAsm::Constraint_T:
return "T";
- case ConstraintCode::Um:
+ case InlineAsm::Constraint_Um:
return "Um";
- case ConstraintCode::Un:
+ case InlineAsm::Constraint_Un:
return "Un";
- case ConstraintCode::Uq:
+ case InlineAsm::Constraint_Uq:
return "Uq";
- case ConstraintCode::Us:
+ case InlineAsm::Constraint_Us:
return "Us";
- case ConstraintCode::Ut:
+ case InlineAsm::Constraint_Ut:
return "Ut";
- case ConstraintCode::Uv:
+ case InlineAsm::Constraint_Uv:
return "Uv";
- case ConstraintCode::Uy:
+ case InlineAsm::Constraint_Uy:
return "Uy";
- case ConstraintCode::X:
+ case InlineAsm::Constraint_X:
return "X";
- case ConstraintCode::Z:
+ case InlineAsm::Constraint_Z:
return "Z";
- case ConstraintCode::ZB:
+ case InlineAsm::Constraint_ZB:
return "ZB";
- case ConstraintCode::ZC:
+ case InlineAsm::Constraint_ZC:
return "ZC";
- case ConstraintCode::Zy:
+ case InlineAsm::Constraint_Zy:
return "Zy";
- case ConstraintCode::p:
+ case InlineAsm::Constraint_p:
return "p";
- case ConstraintCode::ZQ:
+ case InlineAsm::Constraint_ZQ:
return "ZQ";
- case ConstraintCode::ZR:
+ case InlineAsm::Constraint_ZR:
return "ZR";
- case ConstraintCode::ZS:
+ case InlineAsm::Constraint_ZS:
return "ZS";
- case ConstraintCode::ZT:
+ case InlineAsm::Constraint_ZT:
return "ZT";
default:
llvm_unreachable("Unknown memory constraint");
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index 00dba57fcb80227..9944ba15997687a 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm(
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- const InlineAsm::ConstraintCode ConstraintID =
+ unsigned ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
+ assert(ConstraintID != InlineAsm::Constraint_Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM instruction to know about this
@@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm(
assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
- const InlineAsm::ConstraintCode ConstraintID =
+ unsigned ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
OpFlags.setMemConstraint(ConstraintID);
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index d8467e2af8786ec..8cc3391e0d96a3d 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
}
if (F.isMemKind()) {
- const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
+ const unsigned MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 720fc4944161225..738dd10633db6a5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- const InlineAsm::ConstraintCode ConstraintID =
+ unsigned ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
+ assert(ConstraintID != InlineAsm::Constraint_Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this output.
@@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
TLI.getPointerTy(DAG.getDataLayout()) &&
"Memory operands expect pointer values");
- const InlineAsm::ConstraintCode ConstraintID =
+ unsigned ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
+ assert(ConstraintID != InlineAsm::Constraint_Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this input.
@@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
}
if (OpInfo.ConstraintType == TargetLowering::C_Address) {
- const InlineAsm::ConstraintCode ConstraintID =
+ unsigned ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
+ assert(ConstraintID != InlineAsm::Constraint_Unknown &&
"Failed to convert memory constraint code to constraint id.");
InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 91b9d77eed70596..a7873241df62e52 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2101,8 +2101,7 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
// Otherwise, this is a memory operand. Ask the target to select it.
std::vector<SDValue> SelOps;
- const InlineAsm::ConstraintCode ConstraintID =
- Flags.getMemoryConstraintID();
+ unsigned ConstraintID = Flags.getMemoryConstraintID();
if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
report_fatal_error("Could not match memory address. Inline asm"
" failure!");
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index bf1605f06bd88d6..686044ea572ac0d 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment(
}
if (F.isMemKind()) {
- InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
+ const unsigned MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 16ab662ca34aa4f..60a155a86667e89 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -62,7 +62,7 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- InlineAsm::ConstraintCode ConstraintID,
+ unsigned ConstraintID,
std::vector<SDValue> &OutOps) override;
template <signed Low, signed High, signed Scale>
@@ -533,14 +533,13 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) {
#endif
bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
- std::vector<SDValue> &OutOps) {
+ const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::ConstraintCode::m:
- case InlineAsm::ConstraintCode::o:
- case InlineAsm::ConstraintCode::Q:
+ case InlineAsm::Constraint_m:
+ case InlineAsm::Constraint_o:
+ case InlineAsm::Constraint_Q:
// We need to make sure that this one operand does not end up in XZR, thus
// require the address to be in a PointerRegClass register.
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index f2696b6b97593a1..67c344318e0d3ec 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1169,10 +1169,9 @@ class AArch64TargetLowering : public TargetLowering {
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
- InlineAsm::ConstraintCode
- getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+ unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
- return InlineAsm::ConstraintCode::Q;
+ return InlineAsm::Constraint_Q;
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
// followed by llvm_unreachable so we'll leave them unimplemented in
// the backend for now.
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index acd2e4b052b65c9..5f4fab0675824fd 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -331,8 +331,7 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- InlineAsm::ConstraintCode ConstraintID,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
std::vector<SDValue> &OutOps) override;
// Form pairs of consecutive R, S, D, or Q registers.
@@ -5865,22 +5864,23 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
return true;
}
-bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
- std::vector<SDValue> &OutOps) {
+
+bool ARMDAGToDAGISel::
+SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
+ std::vector<SDValue> &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::ConstraintCode::m:
- case InlineAsm::ConstraintCode::o:
- case InlineAsm::ConstraintCode::Q:
- case InlineAsm::ConstraintCode::Um:
- case InlineAsm::ConstraintCode::Un:
- case InlineAsm::ConstraintCode::Uq:
- case InlineAsm::ConstraintCode::Us:
- case InlineAsm::ConstraintCode::Ut:
- case InlineAsm::ConstraintCode::Uv:
- case InlineAsm::ConstraintCode::Uy:
+ case InlineAsm::Constraint_m:
+ case InlineAsm::Constraint_o:
+ case InlineAsm::Constraint_Q:
+ case InlineAsm::Constraint_Um:
+ case InlineAsm::Constraint_Un:
+ case InlineAsm::Constraint_Uq:
+ case InlineAsm::Constraint_Us:
+ case InlineAsm::Constraint_Ut:
+ case InlineAsm::Constraint_Uv:
+ case InlineAsm::Constraint_Uy:
// Require the address to be in a register. That is safe for all ARM
// variants and it is hard to do anything much smarter without knowing
// how the operand is used.
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index efa82386768605d..2dd54602ef61b9c 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -534,29 +534,29 @@ class VectorType;
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
- InlineAsm::ConstraintCode
+ unsigned
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
- return InlineAsm::ConstraintCode::Q;
- if (ConstraintCode.size() == 2) {
+ return InlineAsm::Constraint_Q;
+ else if (ConstraintCode.size() == 2) {
if (ConstraintCode[0] == 'U') {
switch(ConstraintCode[1]) {
default:
break;
case 'm':
- return InlineAsm::ConstraintCode::Um;
+ return InlineAsm::Constraint_Um;
case 'n':
- return InlineAsm::ConstraintCode::Un;
+ return InlineAsm::Constraint_Un;
case 'q':
- return InlineAsm::ConstraintCode::Uq;
+ return InlineAsm::Constraint_Uq;
case 's':
- return InlineAsm::ConstraintCode::Us;
+ return InlineAsm::Constraint_Us;
case 't':
- return InlineAsm::ConstraintCode::Ut;
+ return InlineAsm::Constraint_Ut;
case 'v':
- return InlineAsm::ConstraintCode::Uv;
+ return InlineAsm::Constraint_Uv;
case 'y':
- return InlineAsm::ConstraintCode::Uy;
+ return InlineAsm::Constraint_Uy;
}
}
}
diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
index 214799aa31a9c7f..bbb1de40be63409 100644
--- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
@@ -43,8 +43,7 @@ class AVRDAGToDAGISel : public SelectionDAGISel {
bool selectIndexedLoad(SDNode *N);
unsigned selectIndexedProgMemLoad(const LoadSDNode *LD, MVT VT, int Bank);
- bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- InlineAsm::ConstraintCode ConstraintCode,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
std::vector<SDValue> &OutOps) override;
// Include the pieces autogenerated from the target description.
@@ -201,10 +200,9 @@ unsigned AVRDAGToDAGISel::selectIndexedProgMemLoad(const LoadSDNode *LD, MVT VT,
}
bool AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, InlineAsm::ConstraintCode ConstraintCode,
- std::vector<SDValue> &OutOps) {
- assert((ConstraintCode == InlineAsm::ConstraintCode::m ||
- ConstraintCode == InlineAsm::ConstraintCode::Q) &&
+ const SDValue &Op, unsigned ConstraintCode, std::vector<SDValue> &OutOps) {
+ assert((ConstraintCode == InlineAsm::Constraint_m ||
+ ConstraintCode == InlineAsm::Constraint_Q) &&
"Unexpected asm memory constraint");
MachineRegisterInfo &RI = MF->getRegInfo();
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 4f5a48bd05a4e86..2b7370409085165 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -2521,13 +2521,13 @@ AVRTargetLowering::getConstraintType(StringRef Constraint) const {
return TargetLowering::getConstraintType(Constraint);
}
-InlineAsm::ConstraintCode
+unsigned
AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
// Not sure if this is actually the right thing to do, but we got to do
// *something* [agnat]
switch (ConstraintCode[0]) {
case 'Q':
- return InlineAsm::ConstraintCode::Q;
+ return InlineAsm::Constraint_Q;
}
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
}
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.h b/llvm/lib/Target/AVR/AVRISelLowering.h
index 6815b519bebf74d..b696bebe7136f42 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.h
+++ b/llvm/lib/Target/AVR/AVRISelLowering.h
@@ -133,8 +133,7 @@ class AVRTargetLowering : public TargetLowering {
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override;
- InlineAsm::ConstraintCode
- getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
+ unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
std::vector<SDValue> &Ops,
diff --git a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
index 1a3c9f14c1d5a8b..32fa4ea1e302b68 100644
--- a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
@@ -48,8 +48,7 @@ class CSKYDAGToDAGISel : public SelectionDAGISel {
SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
- bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- InlineAsm::ConstraintCode ConstraintID,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
std::vector<SDValue> &OutOps) override;
#include "CSKYGenDAGISel.inc"
@@ -384,10 +383,9 @@ SDNode *CSKYDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
}
bool CSKYDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
- std::vector<SDValue> &OutOps) {
+ const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
switch (ConstraintID) {
- case InlineAsm::ConstraintCode::m:
+ case InlineAsm::Constraint_m:
// We just support simple memory operands that have a single address
// operand and need no special handling.
OutOps.push_back(Op);
diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
index c400c9a3fc992f9..e33654ea3f18665 100644
--- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
+++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
@@ -227,8 +227,7 @@ class M68kDAGToDAGISel : public SelectionDAGISel {
bool SelectPCD(SDNode *Parent, SDValue N, SDValue &Imm);
bool SelectPCI(SDNode *Parent, SDValue N, SDValue &Imm, SDValue &Index);
- bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- InlineAsm::ConstraintCode ConstraintID,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
std::vector<SDValue> &OutOps) override;
// If Address Mode represents Frame Index store FI in Disp and
@@ -954,8 +953,7 @@ bool M68kDAGToDAGISel::SelectARI(SDNode *Parent, SDValue N, SDValue &Base) {
}
bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
- std::vector<SDValue> &OutOps) {
+ const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
// In order to tell AsmPrinter the exact addressing mode we select here, which
// might comprise of multiple SDValues (hence MachineOperands), a 32-bit
// immediate value is prepended to the list of selected SDValues to indicate
@@ -968,7 +966,7 @@ bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand(
switch (ConstraintID) {
// Generic memory operand.
- case InlineAsm::ConstraintCode::m: {
+ case InlineAsm::Constraint_m: {
// Try every supported (memory) addressing modes.
SDValue Operands[4];
@@ -999,7 +997,7 @@ bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand(
return true;
}
// 'Q': Address register indirect addressing.
- case InlineAsm::ConstraintCode::Q: {
+ case InlineAsm::Constraint_Q: {
SDValue AMKind, Base;
// 'j' addressing mode.
// TODO: Add support for 'o' and 'e' after their
@@ -1011,7 +1009,7 @@ bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand(
return true;
}
// 'U': Address register indirect w/ constant offset addressing.
- case InlineAsm::ConstraintCode::Um: {
+ case InlineAsm::Constraint_Um: {
SDValue AMKind, Base, Offset;
// 'p' addressing mode.
if (SelectARID(nullptr, Op, Offset, Base) && addKind(AMKind, AMK::p)) {
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
index 82f6d7323cf60b4..ae3c348a59999e1 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -204,12 +204,11 @@ M68kTargetLowering::getExceptionSelectorRegister(const Constant *) const {
return M68k::D1;
}
-InlineAsm::ConstraintCode
+unsigned
M68kTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
- return StringSwitch<InlineAsm::ConstraintCode>(ConstraintCode)
- .Case("Q", InlineAsm::ConstraintCode::Q)
- // We borrow ConstraintCode::Um for 'U'.
- .Case("U", InlineAsm::ConstraintCode::Um)
+ return StringSwitch<unsigned>(ConstraintCode)
+ .Case("Q", InlineAsm::Constraint_Q)
+ .Case("U", InlineAsm::Constraint_Um) // We borrow Constraint_Um for 'U'.
.Default(TargetLowering::getInlineAsmMemConstraint(ConstraintCode));
}
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.h b/llvm/lib/Target/M68k/M68kISelLowering.h
index 37e66695fde9036..5f279b3dcbd3ee4 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.h
+++ b/llvm/lib/Target/M68k/M68kISelLowering.h
@@ -187,8 +187,7 @@ class M68kTargetLowering : public TargetLowering {
Register
getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
- InlineAsm::ConstraintCode
- getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
+ unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
private:
unsigned GetAlignedArgumentStackSize(unsigned StackSize,
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index d5c1ab4718dbdf4..c6cefc000b3f746 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2163,13 +2163,12 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
}
bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
- std::vector<SDValue> &OutOps) {
+ const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
// Always produce a register and immediate operand, as expected by
// RISCVAsmPrinter::PrintAsmMemoryOperand.
switch (ConstraintID) {
- case InlineAsm::ConstraintCode::o:
- case InlineAsm::ConstraintCode::m: {
+ case InlineAsm::Constraint_o:
+ case InlineAsm::Constraint_m: {
SDValue Op0, Op1;
bool Found = SelectAddrRegImm(Op, Op0, Op1);
assert(Found && "SelectAddrRegImm should always succeed");
@@ -2178,7 +2177,7 @@ bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
OutOps.push_back(Op1);
return false;
}
- case InlineAsm::ConstraintCode::A:
+ case InlineAsm::Constraint_A:
OutOps.push_back(Op);
OutOps.push_back(
CurDAG->getTargetConstant(0, SDLoc(Op), Subtarget->getXLenVT()));
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index b9117a4c5efeaa4..fbc1520a54ba071 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -43,8 +43,7 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
void Select(SDNode *Node) override;
- bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- InlineAsm::ConstraintCode ConstraintID,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
std::vector<SDValue> &OutOps) override;
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a89961dccc70f3d..a470ceae90ce591 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17418,13 +17418,13 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
return Res;
}
-InlineAsm::ConstraintCode
+unsigned
RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
// Currently only support length 1 constraints.
if (ConstraintCode.size() == 1) {
switch (ConstraintCode[0]) {
case 'A':
- return InlineAsm::ConstraintCode::A;
+ return InlineAsm::Constraint_A;
default:
break;
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index e4481a0f6752fa3..461b929643f2688 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -566,8 +566,7 @@ class RISCVTargetLowering : public TargetLowering {
ConstraintType getConstraintType(StringRef Constraint) const override;
- InlineAsm::ConstraintCode
- getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
+ unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index fed26111f60ec65..5ebb0a8239aa38b 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -259,7 +259,7 @@ namespace {
/// Implement addressing mode selection for inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- InlineAsm::ConstraintCode ConstraintID,
+ unsigned ConstraintID,
std::vector<SDValue> &OutOps) override;
void emitSpecialCodeForMain();
@@ -6323,18 +6323,18 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
SelectCode(Node);
}
-bool X86DAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
- std::vector<SDValue> &OutOps) {
+bool X86DAGToDAGISel::
+SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
+ std::vector<SDValue> &OutOps) {
SDValue Op0, Op1, Op2, Op3, Op4;
switch (ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::ConstraintCode::o: // offsetable ??
- case InlineAsm::ConstraintCode::v: // not offsetable ??
- case InlineAsm::ConstraintCode::m: // memory
- case InlineAsm::ConstraintCode::X:
- case InlineAsm::ConstraintCode::p: // address
+ case InlineAsm::Constraint_o: // offsetable ??
+ case InlineAsm::Constraint_v: // not offsetable ??
+ case InlineAsm::Constraint_m: // memory
+ case InlineAsm::Constraint_X:
+ case InlineAsm::Constraint_p: // address
if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
return true;
break;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 4d45a0a58442105..5689543fcd1fa2c 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -1279,10 +1279,10 @@ namespace llvm {
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
- InlineAsm::ConstraintCode
+ unsigned
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "v")
- return InlineAsm::ConstraintCode::v;
+ return InlineAsm::Constraint_v;
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
}
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