[PATCH] D158368: [AMDGPU][MISCHED] GCNBalancedSchedStrategy.

[Alexander via Phabricator via llvm-commits]

alex-t updated this revision to Diff 556666.
alex-t added a comment.

Changed the criteria for reverting current stage schedule and for the HighOccupancyRPStage running on region


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158368/new/

https://reviews.llvm.org/D158368

Files:
  llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
  llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
  llvm/test/CodeGen/AMDGPU/bf16.ll
  llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
  llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
  llvm/test/CodeGen/AMDGPU/function-args.ll
  llvm/test/CodeGen/AMDGPU/function-returns.ll
  llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
  llvm/test/CodeGen/AMDGPU/half.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
  llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
  llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
  llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
  llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
  llvm/test/CodeGen/AMDGPU/load-global-i16.ll
  llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
  llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
  llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D158368.556666.patch
Type: text/x-patch
Size: 519100 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230913/ce0ebcb1/attachment-0001.bin>