[llvm] [SelectionDAG] NFC: Add target hooks to enable vector coercion in CopyToReg / CopyFromReg (PR #66134)

[Jeffrey Byrnes via llvm-commits]

https://github.com/jrbyrnes updated https://github.com/llvm/llvm-project/pull/66134:

>From 5dcf1478671bbfc8caaa691daf777866a0d7e181 Mon Sep 17 00:00:00 2001
From: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
Date: Tue, 12 Sep 2023 13:02:45 -0700
Subject: [PATCH] [SelectionDAG] NFC: Add target hooks to enable vector
 coercion in CopyToReg / CopyFromReg

Change-Id: I7c888ad2c3cd7f1104aed47725852e2fe09b7665
---
 llvm/include/llvm/CodeGen/TargetLowering.h    | 20 ++++++++++++++-----
 .../SelectionDAG/SelectionDAGBuilder.cpp      |  9 +++++++++
 2 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 12b280d5b1a0bcd..4066fccf2312abe 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -1076,10 +1076,10 @@ class TargetLoweringBase {
   /// This method returns the number of registers needed, and the VT for each
   /// register.  It also returns the VT and quantity of the intermediate values
   /// before they are promoted/expanded.
-  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
-                                  EVT &IntermediateVT,
-                                  unsigned &NumIntermediates,
-                                  MVT &RegisterVT) const;
+  virtual unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
+                                          EVT &IntermediateVT,
+                                          unsigned &NumIntermediates,
+                                          MVT &RegisterVT) const;
 
   /// Certain targets such as MIPS require that some types such as vectors are
   /// always broken down into scalars in some contexts. This occurs even if the
@@ -1091,6 +1091,16 @@ class TargetLoweringBase {
                                   RegisterVT);
   }
 
+  /// Certain targets, such as AMDGPU, may coerce vectors of one type to another
+  /// to produce optimal code for CopyToReg / CopyFromReg pairs when dealing
+  /// with non-legal types -- e.g. v7i8 -> v2i32. This gives targets an
+  /// opportunity to do custom lowering in such cases.
+  virtual SDValue lowerVectorCopyReg(bool ISABIRegCopy, SelectionDAG &DAG,
+                                     const SDLoc &DL, SDValue &Val, EVT Source,
+                                     EVT Dest, bool IsCopyTo = true) const {
+    return SDValue();
+  };
+
   struct IntrinsicInfo {
     unsigned     opc = 0;          // target opcode
     EVT          memVT;            // memory VT
@@ -1598,7 +1608,7 @@ class TargetLoweringBase {
   }
 
   /// Return the type of registers that this ValueType will eventually require.
-  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
+  virtual MVT getRegisterType(LLVMContext &Context, EVT VT) const {
     if (VT.isSimple())
       return getRegisterType(VT.getSimpleVT());
     if (VT.isVector()) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 5a227ba398e1c11..afa6caae889dabb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -400,6 +400,11 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
     if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
       return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
 
+    if (auto TargetLowered = TLI.lowerVectorCopyReg(IsABIRegCopy, DAG, DL, Val,
+                                                    PartEVT, ValueVT, false)) {
+      // Give targets a chance to custom lower mismatched sizes
+      return TargetLowered;
+    }
     // If the parts vector has more elements than the value vector, then we
     // have a vector widening case (e.g. <2 x float> -> <4 x float>).
     // Extract the elements we want.
@@ -765,6 +770,10 @@ static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL,
   } else if (ValueVT.getSizeInBits() == BuiltVectorTy.getSizeInBits()) {
     // Bitconvert vector->vector case.
     Val = DAG.getNode(ISD::BITCAST, DL, BuiltVectorTy, Val);
+  } else if (SDValue TargetLowered = TLI.lowerVectorCopyReg(
+                 IsABIRegCopy, DAG, DL, Val, ValueVT, BuiltVectorTy)) {
+    // Give targets a chance to custom lower mismatched sizes
+    Val = TargetLowered;
   } else {
     if (BuiltVectorTy.getVectorElementType().bitsGT(
             ValueVT.getVectorElementType())) {