[llvm] [RISCV] Reduce LMUL when index is known when lowering insert_vector_elt (PR #66087)

[Luke Lau via llvm-commits]

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@@ -550,9 +550,9 @@ define void @insertelt_c6_v8i64_0_add(ptr %x, ptr %y) {
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    li a2, 6
-; CHECK-NEXT:    vsetvli zero, zero, e64, m4, tu, ma
+; CHECK-NEXT:    vsetivli zero, 8, e64, m1, tu, ma
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lukel97 wrote:

Here's what I think is happening: VL was already set to 8 before this patch, see the vsetvli a couple of instructions above, which is correct at zvl128b and LMUL=4 for v8i64. Presumably the existing lowering code uses VL=8 even for the vmv.s.x to avoid a vl toggle.

Previously the vmv.s.x and vle64.v had the same SEW/LMUL ratio and thus the same VLMAX, so RISCVInsertVSETVLI emitted the x0, x0 form of vsetvli when it noticed that VL didn't need to change:

https://github.com/llvm/llvm-project/blob/c8d405323e2f7c4ce6d65168ad8e79f669feece2/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp#L878-L895

But now the SEW/LMUL ratio is different, hence why it no longer emits it that way. Should we go out of our way to drop 8 down to 1 just for the vmv.s.x? 

https://github.com/llvm/llvm-project/pull/66087