[llvm] b2f1a1b - [RISCV] Move getSmallestVTForIndex so it can be used by lowerINSERT_VECTOR_ELT. NFC

[Luke Lau via llvm-commits]

Author: Luke Lau
Date: 2023-09-12T15:58:19+01:00
New Revision: b2f1a1b20b7c5be30e9718a586741679de6eab4c

URL: https://github.com/llvm/llvm-project/commit/b2f1a1b20b7c5be30e9718a586741679de6eab4c
DIFF: https://github.com/llvm/llvm-project/commit/b2f1a1b20b7c5be30e9718a586741679de6eab4c.diff

LOG: [RISCV] Move getSmallestVTForIndex so it can be used by lowerINSERT_VECTOR_ELT. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1158d14002e1d2a..0dd03076cc05b36 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7345,6 +7345,32 @@ RISCVTargetLowering::lowerVectorFPExtendOrRoundLike(SDValue Op,
   return Result;
 }
 
+// Given a scalable vector type and an index into it, returns the type for the
+// smallest subvector that the index fits in. This can be used to reduce LMUL
+// for operations like vslidedown.
+//
+// E.g. With Zvl128b, index 3 in a nxv4i32 fits within the first nxv2i32.
+static std::optional<MVT>
+getSmallestVTForIndex(MVT VecVT, unsigned MaxIdx, SDLoc DL, SelectionDAG &DAG,
+                      const RISCVSubtarget &Subtarget) {
+  assert(VecVT.isScalableVector());
+  const unsigned EltSize = VecVT.getScalarSizeInBits();
+  const unsigned VectorBitsMin = Subtarget.getRealMinVLen();
+  const unsigned MinVLMAX = VectorBitsMin / EltSize;
+  MVT SmallerVT;
+  if (MaxIdx < MinVLMAX)
+    SmallerVT = getLMUL1VT(VecVT);
+  else if (MaxIdx < MinVLMAX * 2)
+    SmallerVT = getLMUL1VT(VecVT).getDoubleNumVectorElementsVT();
+  else if (MaxIdx < MinVLMAX * 4)
+    SmallerVT = getLMUL1VT(VecVT)
+                    .getDoubleNumVectorElementsVT()
+                    .getDoubleNumVectorElementsVT();
+  if (!SmallerVT.isValid() || !VecVT.bitsGT(SmallerVT))
+    return std::nullopt;
+  return SmallerVT;
+}
+
 // Custom-legalize INSERT_VECTOR_ELT so that the value is inserted into the
 // first position of a vector, and that vector is slid up to the insert index.
 // By limiting the active vector length to index+1 and merging with the
@@ -7466,32 +7492,6 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
   return convertFromScalableVector(VecVT, Slideup, DAG, Subtarget);
 }
 
-// Given a scalable vector type and an index into it, returns the type for the
-// smallest subvector that the index fits in. This can be used to reduce LMUL
-// for operations like vslidedown.
-//
-// E.g. With Zvl128b, index 3 in a nxv4i32 fits within the first nxv2i32.
-static std::optional<MVT>
-getSmallestVTForIndex(MVT VecVT, unsigned MaxIdx, SDLoc DL, SelectionDAG &DAG,
-                      const RISCVSubtarget &Subtarget) {
-  assert(VecVT.isScalableVector());
-  const unsigned EltSize = VecVT.getScalarSizeInBits();
-  const unsigned VectorBitsMin = Subtarget.getRealMinVLen();
-  const unsigned MinVLMAX = VectorBitsMin / EltSize;
-  MVT SmallerVT;
-  if (MaxIdx < MinVLMAX)
-    SmallerVT = getLMUL1VT(VecVT);
-  else if (MaxIdx < MinVLMAX * 2)
-    SmallerVT = getLMUL1VT(VecVT).getDoubleNumVectorElementsVT();
-  else if (MaxIdx < MinVLMAX * 4)
-    SmallerVT = getLMUL1VT(VecVT)
-                    .getDoubleNumVectorElementsVT()
-                    .getDoubleNumVectorElementsVT();
-  if (!SmallerVT.isValid() || !VecVT.bitsGT(SmallerVT))
-    return std::nullopt;
-  return SmallerVT;
-}
-
 // Custom-lower EXTRACT_VECTOR_ELT operations to slide the vector down, then
 // extract the first element: (extractelt (slidedown vec, idx), 0). For integer
 // types this is done using VMV_X_S to allow us to glean information about the