[llvm] [AArch64][SME] Various tests should work with +sme, just as they do for +sve (PR #65260)

[via llvm-commits]

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@@ -6202,7 +6202,7 @@ bool AArch64TargetLowering::useSVEForFixedLengthVectorVT(
 
   // All SVE implementations support NEON sized vectors.
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paulwalker-arm wrote:

I'm not sure we want to go overboard with giving the impression SME is distinct from SVE because the nuances are going to confuse people, with this a prime example.  Whilst SVE does truly support NEON size vectors, the same is not true for SME where the support is simulated though the use of predication.  In general when we mean "SVE instructions" I'd rather we just say SVE and then better document the SVE instructions that are not provided by SME, which are significant fewer in number.

https://github.com/llvm/llvm-project/pull/65260