[llvm] [RISCV] Fix internal compiler about Zcmp. (PR #66073)
Yeting Kuo via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 12 05:13:06 PDT 2023
https://github.com/yetingk created https://github.com/llvm/llvm-project/pull/66073:
The original code encounters ICE when we need to spill callee saves but none of them is GPR.
>From bf518a62147d7ae94fc6860fb117815c2cc76d09 Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Tue, 12 Sep 2023 20:06:06 +0800
Subject: [PATCH] [RISCV] Fix internal compiler about Zcmp.
The original code encounters ICE when we need to spill callee saves but none of
them is GPR.
---
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 10 +++++-----
llvm/test/CodeGen/RISCV/zcmp-crash.ll | 21 ++++++++++++++++++++
2 files changed, 26 insertions(+), 5 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/zcmp-crash.ll
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index add933250f8473d..898412ff446b075 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -1371,12 +1371,12 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
RISCVMachineFunctionInfo *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
if (RVFI->isPushable(*MF)) {
Register MaxReg = getMaxPushPopReg(*MF, CSI);
- unsigned PushedRegNum =
- getPushPopEncoding(MaxReg) - llvm::RISCVZC::RLISTENCODE::RA + 1;
- RVFI->setRVPushRegs(PushedRegNum);
- RVFI->setRVPushStackSize(alignTo((STI.getXLen() / 8) * PushedRegNum, 16));
-
if (MaxReg != RISCV::NoRegister) {
+ unsigned PushedRegNum =
+ getPushPopEncoding(MaxReg) - llvm::RISCVZC::RLISTENCODE::RA + 1;
+ RVFI->setRVPushRegs(PushedRegNum);
+ RVFI->setRVPushStackSize(alignTo((STI.getXLen() / 8) * PushedRegNum, 16));
+
// Use encoded number to represent registers to spill.
unsigned RegEnc = getPushPopEncoding(MaxReg);
RVFI->setRVPushRlist(RegEnc);
diff --git a/llvm/test/CodeGen/RISCV/zcmp-crash.ll b/llvm/test/CodeGen/RISCV/zcmp-crash.ll
new file mode 100644
index 000000000000000..b22085f95a3d1b0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zcmp-crash.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+f,+zcmp -verify-machineinstrs < %s | FileCheck %s
+
+; Test the file could be compiled successfully.
+define void @bar() {
+; CHECK-LABEL: bar:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset fs0, -4
+; CHECK-NEXT: #APP
+; CHECK-NEXT: fmv.w.x fs0, zero
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+entry:
+ tail call void asm sideeffect "fmv.w.x fs0, zero", "~{fs0}"()
+ ret void
+}
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